Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-08-27
2009-06-16
Nguyen, Tuan T (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189080, C365S233190
Reexamination Certificate
active
07548485
ABSTRACT:
A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.
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Kim Young-Seung
Park Chul-Sung
Nguyen Hien N
Nguyen Tuan T
Samsung Electronics Co,. Ltd.
Volentine & Whitt P.L.L.C.
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