Semiconductor memory device bonding pad arrangement

Details Semiconductor memory device bonding pad arrangement Semiconductor memory device bonding pad arrangement

1994-06-10

1995-12-05

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257676, 257686, H01L 2348

Patent

active

054731984

ABSTRACT:
A semiconductor memory device having inner lead portions of a plurality of leads disposed through at least one insulating film on a semiconductor chip and electrically insulated from the semiconductor chip, includes bonding pads for at least data input/output arranged in two rows axially symmetrically in a substantially central portion of the semiconductor chip interposed between memory arrays and bonding wires for connecting the inner lead portions and the bonding pads.

REFERENCES:
patent: 5068712 (1991-11-01), Murakami et al.
patent: 5165067 (1992-11-01), Wakefield et al.
patent: 5365113 (1994-11-01), Sakuta et al.

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