Semiconductor memory device being coupled by auxiliary power lin

Details Semiconductor memory device being coupled by auxiliary power lin Semiconductor memory device being coupled by auxiliary power lin

1991-05-20

1994-06-14

Lee, Benny

Static information storage and retrieval

Read/write circuit

Noise suppression

365226, G11C 514

Patent

active

053216580

ABSTRACT:
In semiconductor memory device having a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells are connected is amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells are connected via a power supply line to a power supply, the adverse effects due to the resistance of the power supply line is eliminated or reduced. This is achieved by coupling a power supply auxiliary line disposed within each memory cell array and a power supply main line disposed along the memory cell arrays by means of a resistive element having a resistance larger than the resistance of the power supply main line from the power supply to the memory cell array located farthest. Alternatively, the common node in each memory cell array is connected to said power supply main line via a resistive element and a sense amplifier drive transistor which is turned on and off by a control signal. Still alternatively, the transistors which are turned on by a control signal to connect the sense amplifiers to a power supply main line have a different mutual conductance depending on the resistance of the power supply line.

REFERENCES:
patent: 3621302 (1971-11-01), Pricer
patent: 4539659 (1985-09-01), Dumont
patent: 5173873 (1992-12-01), Komatsu et al.
Ananomyous Author; "Method For Equalizing Chip Power Flow"; Reproduced from Research Disclosure; Apr. 1986, No. 264.

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