Semiconductor memory device asynchronously communicable with ext

Static information storage and retrieval – Read/write circuit – Signals

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365191, 36518904, G11C 700

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06023430&

ABSTRACT:
Data is asynchronously transferred between a semiconductor static random access memory device and an external device equipped with an asynchronous access controller by using an access request signal representative of a request for accessing data bits stored in the semiconductor static random access memory device and an acknowledge signal representative of completion of the data access, and Muller's c-elements are incorporated in the asynchronous access controller for producing the access request signal at more than one timing in each access cycle under the control of two clock signals different in phase from each other.

REFERENCES:
patent: 5673398 (1997-09-01), Takeda
Nanya et al., "Asynchronous Processors--Toward Ultrahigh-Speed VLSI Systems", (partial translation),Information Processing, vol. 34, No. 1, Jan. 1993, p. 76.
Takamura et al., "Performance Enhancement Technologies in Logic Design of Asynchronous Processor TITAC-2", (partial trans.), Papers Elec. Info. Comm. Soc. D-1, vol. J80-D-1, (Mar. 1997), pp. 189-196.
Komori et al., "A 50MFLOPS Superpipelined Data-Driven Microprocessor", 1991 IEEE International Solid State Circuits Conference, pp. 92-93.
Meng et al., "Automatic Synthesis of Asynchrous Circuits from High-Level Specifications", IEEE Transactions on Computer-aided Design, vol. 8, No. 11, (Nov. 1989), pp. 1185-1205.
Williams et al., "A Zero-Overhead Self-Timed 160ns 54b CMOS Divider", 1991 IEEE International Solid State Circuits Conference, pp. 98-99.

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