Semiconductor memory device associated with peripheral logic gat

Details Semiconductor memory device associated with peripheral logic gat Semiconductor memory device associated with peripheral logic gat

1990-09-06

1992-06-23

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Signals

36518901, G11C 700

Patent

active

051249464

ABSTRACT:
A semiconductor memory device is associated with peripheral logic gates producing at least an address signal representative of an address, a write-in enable signal and an input data signal indicative of a piece of data information, and the peripheral logic gates selectively enters an usual mode of operation and a scan-path diagnostic mode of operation, wherein the semiconductor memory device comprises a memory cell array having a plurality of memory cells each having an address and memorizing a piece of data information, and peripheral circuits having a write-in controlling circuit supplying a write-in controlling signal to the memory cell array for allowing the piece of data information to be memorized in one of the memory cells designated by the address signal and a prohibiting circuit operative to prohibit the write-in controlling circuit from supplying the write-in controlling signal in the diagnostic mode of operation, thereby preventing pieces of data information memorized in the memory cell array from destruction.

REFERENCES:
patent: 4707809 (1987-11-01), Ando

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