Semiconductor memory device and writing method thereof

Details Semiconductor memory device and writing method thereof Semiconductor memory device and writing method thereof

2008-06-24

2008-06-24

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Amorphous

C365S189020, C365S189070, C365S190000

Reexamination Certificate

active

07391643

ABSTRACT:
To provide a semiconductor memory device comprising a phase-change memory and having high compatibility with DRAM interface. The memory cell array18comprises a memory cell that includes a phase-change element provided at the intersection of a bit line and word line. A write address and data accompanying a write request are temporarily held in a write address register15and a data register14respectively, and a write operation is not performed on the memory cell array18in this cycle of write request. And when a next write request occurs, the held data is written to the memory cell array18. At this time, two write cycles—RESET cycle and SET cycle—are provided. Then the written contents of the memory cell and the rewrite data are compared, and after only SET cells are temporarily RESET (amorphization, increasing the resistance), it is operated so as to write only SET data (crystallization, lowering the resistance).

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