Semiconductor memory device and write driving thereof

Details Semiconductor memory device and write driving thereof Semiconductor memory device and write driving thereof

2001-10-25

2003-06-03

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S230060

Reexamination Certificate

active

06574151

ABSTRACT:

TECHNICAL FIELD
A semiconductor memory device and, more particularly, to a write driving in a semiconductor memory device are disclosed.
DESCRIPTION OF THE RELATED ART
In the case of DRAM, address terminal signals are acknowledged as raw-address signals and input to an internal circuit as soon as raw-address-strobe (/RAS) signals are activated. Certain word lines become enabled by the raw address signals and the bit line pairs of a plurality of memory cells connected to the word lines are amplified by a sense amplifier. Then, when column-address-strobe (/CAS) signals are activated, the address terminal signals are acknowledged as column address signals and input to the internal circuit. After that, a column decoder is enabled and the memory cell of a column is selected from a number of memory cells.
Write-enable (/WE) signals are activated immediately before the column of a certain memory cell is selected to inform the DRAM that the corresponding cycle is a write operation. When a certain column is selected, the write data are loaded on data bus lines by a write driver and the electric potential of the data bus lines is transferred to the bit lines of the selected column.
Meanwhile, to perform the memory access (read/write) operation following the corresponding write operation continuously within a short time, the write path may be precharged by precharging the potential of the data bus line as soon as possible.
The time taken to precharge the databus is commonly referred to as the write recovery time. As the write recovery time increases, the time for a new memory access operation increases, which limits the high-speed operation of the memory device.
In the case that the input data are opposite to the current bus data (i.e., bit line potential) stored in the memory cell in a conventional write driving system, the bit line data are inverted during the enable period of the column selection signals, which are of short pulse, and after the column selection signals are disabled. The bit line sense amplifier drives the potential of the bit line pairs to the cell power supply voltage (Vcc) and the ground voltage (Vss) independently. Thus, the driving power of the sense amplifier affects the write-recovery time.
FIG. 1
is a block diagram showing the write path of a semiconductor memory device in accordance with a conventional method. As shown in
FIG. 1
, the write path of a conventional semiconductor memory device includes a memory cell
19
, a sense amplifier
18
for driving the bit lines of the memory cell
19
to the pull-up and pull-down power, a sense amplifier power driving unit
16
for providing cell power supply voltage (Vcc) as a pull-up power of the sense amplifier
18
and ground voltage (Vss) as its pull-down power, a sense amplifier power driving control unit
14
for generating pull-up and pull-down control signals (Pu, Pd) for controlling the sense amplifier power driving unit
16
in response to the RAS signals, a write control unit
10
for generating write control signals in response to the write command, and a write driving unit
12
for driving the input terminal of the sense amplifier
18
to a level corresponding to the input data in response to the write control signals.
FIG. 2
is a circuit diagram depicting the power driving unit of the sense amplifier of FIG.
1
. Referring to
FIG. 2
, the sense amplifier power driving unit
16
includes a pull-up power driving unit
20
for driving the pull-up power terminal of the sense amplifier
18
to a cell power supply voltage (Vcc) with the control of the pull-up control signal (Pu), and a pull-down power driving unit
24
for driving the pull-down power terminal of the sense amplifier
18
to a ground voltage (Vss) with the control of the pull-down control signal (Pd). The pull-up power driving unit
20
includes an NMOS transistor, of which the gate receives the pull-up control signal (Pu) connected between the cell power supply voltage (Vcc) and the pull-up power terminal of the sense amplifier
18
. The pull-down power driving unit
24
consists of an NMOS transistor, pull-down control signals (Pd), connected between the ground voltage (Vss) and the pull-down power terminal of the sense amplifier
18
.
As described above, the sense amplifier power driving unit
16
provides the cell power supply voltage (Vcc) as the pull-up power of the sense amplifier
18
and the ground voltage (Vss) as its pull-down power according to the status of RAS signals, regardless of the reception of write commands during the entire period when the RAS signals are activated.
FIG. 3
illustrates waveforms of the write operation of the semiconductor memory device in accordance with a conventional method. Referring to
FIG. 3
, if RAS signals are synchronized with the rising edge of external clock signals (CLK) and become activated, pull-up control signals (Pu) and pull-down control signals (Pd) are activated. Then, the sense amplifier power driving unit
16
receives the pull-up control signals (Pu) and the pull-down control signals (Pd) and outputs cell power supply voltage (Vcc) and ground voltage (Vss) as pull-up and pull-down power, respectively. Subsequently, the sense amplifier
18
drives bit line pairs (BL or /BL) to the cell power supply voltage (Vcc) and ground voltage (Vss) according to the signals received. Meanwhile, the potential of the bit line pairs (BL or /BL) selected by the write driving unit
12
are inverted when column signals are activated after write commands are input in response to an activation of RAS signals. This is a case where the input data are opposite to the data currently on the corresponding bit lines. The bit line pairs are charged or discharged to cell power supply voltage (Vcc) or ground voltage (Vss) by the operation of the sense amplifier
18
. On the other hand, if the precharge signals are received and the RAS signals are inactivated, the pull-up (Pu) and the pull-down (Pd) control signals also become inactive and the sense amplifier stops the operation.
The conventional semiconductor memory device provides cell power supply voltage (Vcc) as the pull-up power (Pu) and the ground voltage (Vss) as the pull-down power (Pd) during the period when RAS signals are activated, regardless of whether the write command is activated or not. This semiconductor memory device, however, does not have any solution for a case when the driving power of the sense amplifier
18
declines as the cell power supply voltage (Vcc) drops. That is, when it goes into the bit line precharge mode after write operation, the bit lines may not be sufficiently activated to reach the cell power supply voltage (Vcc) before beginning the precharge, which slows the recovery time and deteriorates the electrical properties of the semiconductor memory device.
SUMMARY OF THE DISCLOSURE
In accordance with one aspect of the disclosure, a semiconductor memory device includes a memory cell, a sense amplifying means for driving a bit line during a writing operation in a memory cell, a write driving means for providing data in response to a write command signal, a power driving means for providing a pull-down voltage and a pull-up voltage to the sense amplifying means in response to a bit line activation signal and a write command signal. The power driving means may provide a ground voltage as the pull-down voltage, and the power driving means may selectively provide a high voltage as the pull-up voltage. The high voltage may be higher than the cell power supply voltage by a predetermined level.
In accordance with another aspect of the disclosure, a method of driving a bit line pair during a writing operation for semiconductor memory device comprising memory cells and a sense amplifying means may include the steps of driving two lines of the bit line pair to a ground voltage and a cell power supply voltage, respectively, in response to an activation of the bit line activation signal, and driving the bit line pair to a high voltage in response to a write command signal. The high voltage may be higher than the cell power supply voltage by

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