Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-03-03
2001-03-13
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230030
Reexamination Certificate
active
06201756
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device and write data masking method thereof for preventing unwanted data from being written into memory cells.
2. Description of the Related Art
The SDRAM (Synchronous DRAM) works according to externally applied clock signals and has a higher data transfer rate compared to the asynchronous DRAM. Hence, the development of the SDRAM effectively contributes to improving the operational speed of a computer system. The conventional SDRAM can transfer only a single set of data in a single clock cycle on either the rising or falling edge of the externally applied clock signal. Such conventional data transfer approaches are generally not compatible with the increasing demand for higher operational speed.
In order to resolve such problems there exists another kind of SDRAM that performs the data input and output operations at both the rising and falling edges of a data strobe signal whose period is the same as that of the clock signal in data read and write operations. This device can therefore perform two data input and output operations in one clock period, and is therefore commonly referred to as a double data rate (DDR) SDRAM. Namely, the DDR SDRAM has double the data transfer rate of the conventional SDRAM, which makes it relatively suited for use in advanced computer systems.
The DDR SDRAM is different from the conventional SDRAM in the construction of the memory cell array and in the data access method it uses. In particular, in the DDR SDRAM, the memory cell array block consists of an even numbered memory cell array block and an odd numbered memory cell array block. The memory cells of the even numbered memory cell array block are accessed by even numbered column selection signals generated by an even numbered column decoder. Similarly, the memory cells of the odd numbered memory cell array block are accessed by the odd numbered column selection signals generated by an odd numbered column decoder. Hence, the DDR SDRAM inputs two sets of data in one clock cycle in response to the data strobe signal, and the two sets of data are simultaneously written into the memory cells of the even and odd numbered memory cell array blocks, which are simultaneously accessed by even and odd numbered column selection signals, respectively, generated by the even and odd numbered column decoders.
The DDR SDRAM has a write data masking function for preventing unwanted data from being written into the even and/or odd numbered memory cell arrays. The masking control signals are supplied through two pins provided in the DDR SDRAM. Furthermore, the conventional DDR SDRAM is designed such that the even numbered data may be written only into the even numbered memory cell array block, and the odd numbered data only into the odd numbered memory cell array block. That is, the even numbered data may not be written into the odd numbered memory cell array block, and the odd numbered data may not be written into the even numbered memory cell array block.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device which can mask even numbered and odd numbered write data using one masking control signal.
According to an aspect of the present invention, a semiconductor memory device comprises a memory cell array having even and an odd numbered memory cell array blocks for storing a first and a second data set, respectively, in response to respective even and odd numbered column selection signals, an address generator for generating a column address in response to column addresses of multiple bits, an even and odd numbered column decoder for decoding the column addresses to respectively generate the even and odd numbered column selection signals according to a first and a second masking control signal, a first and a second masking control signal generator for latching a masking control signal in response to data strobe signals of first and second states, respectively, and generating a third and a fourth masking control signal, respectively, in response to a clock signal, in order to generate the third and fourth masking control signals, respectively, as the first and second masking control signals or second and first masking control signals in response to a single bit column address selected from the column addresses of multiple bits, and a first and a second data generator for latching the input data in response to the data strobe signals of the first and second states, respectively, and generating a third and a fourth data set, respectively, in response to the clock signal in order to generate the third and fourth data, respectively, as the first and second data or second and first data in response to the single bit column address.
According to another aspect of the present invention, a method for masking memory cells from writing unwanted data is provided for a semiconductor memory device, which comprises a memory cell array having even and an odd numbered memory cell array blocks for storing a first and a second data according to respective even and odd numbered column selection signals, an address generator for generating column address in response to column address of multiple bits, and an even and an odd numbered column decoder for decoding the column address and generating the even and odd numbered column selection signals in response to a first and a second masking control signals. The method comprises the steps of receiving a masking control signal in response to the data strobe signal of a first state or a second state and respectively generating a third or fourth masking control signal in response to a clock signal while receiving the input data in response to the data strobe signal of the first or second state to respectively generate a third or fourth data in response to the clock signal, and generating the third and fourth masking control signals respectively as the first and second or second and first masking control signals in response to the column address while generating the third and fourth data, respectively, as the first and second or second and first data in response to the column address.
REFERENCES:
patent: 6011745 (2000-01-01), Okamura
patent: 6108265 (2000-08-01), Takeuchi
Fears Terrell W.
Samsung Electronics Co,. Ltd.
Samuels , Gauthier & Stevens, LLP
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