Semiconductor memory device and voltage level control method...

Details Semiconductor memory device and voltage level control method... Semiconductor memory device and voltage level control method...

2001-11-30

2003-03-18

Phan, Trong (Department: 2818)

Static information storage and retrieval

Powering

C365S201000, C365S225700

Reexamination Certificate

active

06535447

ABSTRACT:

RELATED APPLICATION DATA
This application claims the benefit of Korean Patent Application No. 2000-71976, filed on Nov. 30, 2000, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device including voltage generators and a voltage level control method thereof.
2. Description of Related Art
The conventional semiconductor memory device turns on an NMOS transistor responsive to a signal applied from a word line and transmits a data between a memory cell and a bit line. The NMOS transistor normally can not transmit a sufficiently high logic level data between the memory cell and the bit line because the NMOS transistor loses an amount of threshold voltage in transmitting the high logic level data.
To address this problem, semiconductor memory devices usually include a high voltage generator for generating a higher voltage than a power supplying voltage. The high voltage generator enables a word line with the higher voltage.
The high voltage generator in the semiconductor memory device comprises a main high voltage generator operating in both a stand-by and an active mode, and a sub high voltage generator operating only in the active mode.
A normal mode includes both stand-by and active modes, as well as a test mode. The standby mode refers to waiting for any activation of the semiconductor memory device. The active mode refers to activating the semiconductor memory device. The test mode refers to testing the semiconductor memory device after its manufacture and before shipment.
Because a high voltage level drop in the active mode is higher than that in a standby mode, both the main high voltage generator and the sub high voltage generator operate to compensate the level drop of the high voltage level.
When two sub high voltage generators are necessary to enable one word line in the active mode and the semiconductor memory device enters a test mode by enabling four word lines simultaneously, eight sub high voltage generators are necessary. Put differently, when N number of sub high voltage generators are necessary to enable one word line in the normal mode, 4N number of sub high voltage generators are necessary to enable four word lines in the test mode.
Each of the 4N sub high voltage generators is designed by calculating not an ideal but an experimental electric charge and by allowing a little bit of margin to this experimental electric charge. Therefore, the total electric charge of the 4N sub high voltage generators designed in the semiconductor memory device are normally higher than those of an ideal 4N sub high voltage generator. In the normal mode, operating all of the sub high voltage generators is a very rare case such that the sum of applied electric charges is not too high. In the test mode, however, all 4N sub high voltage generators operate resulting in the sum of applied electric charges to be higher than those in the normal mode. The result is that the high voltage level drop does not occur in the case of all 4N sub high voltage generators being fully operational in the test mode of a semiconductor memory device.
High voltage oversupply by the 4N sub high voltage generators can cause a normal semiconductor memory device to be tagged as a failing device by causing a defect error due to the over kill phenomena in the test mode. The conventional semiconductor memory device, therefore, does not have any method to control the number of operational sub high voltage generators in the test mode and cannot verify the necessary number of sub high voltage generators.
The above described problem can occur not only in the high voltage generators, but also in other voltage generators.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the problems associated with prior art semiconductor memory devices.
It is another object to provide a semiconductor memory device that can control the number of sub high voltage generators necessary in both the test and normal modes.
It is yet another object to provide a voltage level control method in the semiconductor memory device for controlling the number of sub high voltage generators necessary in both the test and normal modes.
An embodiment of the semiconductor memory device comprises multiple sub high voltage generators, multiple control apparatus, high voltage level detecting apparatus, and mode setting apparatus. The multiple sub high voltage generators boost the high voltage level. The multiple control apparatus control the corresponding multiple sub high voltage generators responsive to corresponding high voltage detecting signals and to corresponding multiple control signals in the test mode. The high voltage level detecting apparatus enabled by an active signal detects the level drop of a high voltage and generates the high voltage detecting signal. The mode setting apparatus set the state of the multiple control signals responsive to external signals in the test mode.
Another embodiment of the semiconductor memory device comprises multiple voltage generators, multiple control apparatus, voltage level detecting apparatus, and mode setting apparatus. The multiple voltage generators boost the voltage level. The multiple control apparatus control operations of the corresponding multiple voltage generators responsive to corresponding voltage detecting signals and corresponding multiple control signals in the test mode. The voltage level detecting apparatus detect the voltage level drop and generate the voltage detecting signal. The mode setting apparatus sets the state of the multiple control signals responsive to the mode setting control signals in the test mode.
A voltage level control method for a semiconductor memory device is also provided. The voltage level control method comprises applying multiple control signals of the multiple voltage generators from the mode setting apparatus in the test mode of the package state, and operating multiple voltage generators for performing the test responsive to the multiple control signals.


REFERENCES:
patent: 5553021 (1996-09-01), Kubono et al.
patent: 5966339 (1999-10-01), Hsu et al.
patent: 6094395 (2000-07-01), Weinfurtner
patent: 6381188 (2002-04-01), Choi et al.

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