Semiconductor memory device and testing method therefor

Details Semiconductor memory device and testing method therefor Semiconductor memory device and testing method therefor

2002-05-03

2003-06-03

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000, C365S226000

Reexamination Certificate

active

06574159

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. In particular, the present invention relates to a semiconductor memory device of which power consumption in a standby state can be reduced. More particularly, the present invention relates to a configuration for reducing standby current of a semiconductor memory device that includes redundancy circuitry for repairing a defective memory cell through replacement with a redundant or spare memory cell. Furthermore, the present invention relates to a testing method of a low power consumption semiconductor memory device.
2. Description of the Background Art
FIG. 51
schematically shows a configuration of a memory cell of a static random access memory (SRAM).
In
FIG. 51
, the memory cell includes a pair of cross coupled P-channel MOS transistors (insulated gate field effect transistors) PQ
1
and PQ
2
for pulling up, a pair of cross coupled N-channel MOS transistors NQ
1
and NQ
2
for data storage, and a pair of accessing N-channel MOS transistors NQ
3
and NQ
4
.
P-channel MOS transistor PQ
1
is electrically coupled between a memory cell power supply line MVCC and a node ND
1
, and has a gate electrically coupled to a node ND
2
. P-channel MOS transistor PQ
2
is electrically coupled between memory cell power supply line MVCC and node ND
2
, and has a gate electrically coupled to node ND
1
.
N-channel MOS transistor NQ
1
is electrically coupled between node ND
1
and a memory cell ground line MVSS, and has a gate electrically coupled to node ND
2
. N-channel MOS transistor NQ
2
is electrically coupled between node ND
2
and memory cell ground line MVSS, and has a gate electrically coupled to node ND
1
.
N-channel MOS transistor NQ
3
turns ON, in response to the potential of a signal on a word line WL, to electrically couple node ND
1
to a bit line BL. N-channel MOS transistor NQ
4
selectively turns ON, in response to the potential of the signal on word line WL, to electrically couple node ND
2
to a complementary bit line ZBL.
In the SRAM cell shown in
FIG. 51
, MOS transistors PQ
1
and NQ
1
form a CMOS (complementary MOS) inverter. Also, MOS transistors PQ
2
and NQ
2
form a CMOS inverter. MOS transistors PQ
1
, PQ
2
, NQ
1
, and NQ
2
form a CMOS inverter latch circuit.
Data complementary to each other are stored at nodes ND
1
and ND
2
. in the SRAM cell, in a data storage mode, a current path of transferring electric current between memory cell power supply line and MVCC memory cell ground line MVSS via nodes ND
1
and ND
2
is cut off. Thus, the power consumption can be reduced.
The memory cell shown in
FIG. 51
is generally called a “full CMOS memory cell”. Compared to a configuration including pull-up load elements provided to nodes ND
1
and ND
2
, the configuration of the full CMOS memory cell is superior in operational performance and low power consumptionability. For these reasons, the full CMOS memory cells are generally widely used in low power consumption SRAMs.
FIG. 52
schematically shows a plan layout of the SRAM cell shown in FIG.
51
. In
FIG. 52
, since the SRAM cell is the full CMOS cell, there is provided an n-well region for forming P-channel MOS transistors PQ
1
and PQ
2
, and a p-well region for forming N-channel MOS transistors NQ
1
and NQ
2
. In the n-well region, there are formed active regions AA
1
and AA
2
in which P-channel MOS transistors PQ
1
and PQ
2
are formed, respectively. Active regions AA
1
and AA
2
are each formed in an L-shape to be symmetric with respect to a central line vertically extending in between, as viewed in FIG.
52
. Active regions AA
1
and AA
2
are used as p-type impurity regions. On the other hand, in the p-well region, active regions AA
3
and AA
4
are formed in which N-channel MOS transistors NQ
1
and NQ
2
are formed, respectively. Active regions AA
3
and AA
4
are each formed in a reversed L-shape to be symmetric with respect to a center line in between. Active regions AA
3
and AA
4
are used as n-type impurity regions.
A gate electrode interconnection line GA
1
is formed across horizontally-extending regions of active regions AA
1
and AA
3
. On the other hand, a gate electrode interconnection line GA
2
is formed across horizontally-extending regions of active regions AA
2
and AA
4
. Gate electrode interconnection lines GA
1
and GA
2
are formed of, for example, polysilicon interconnection lines. In addition, a gate electrode interconnection line GA
3
is formed across vertically extending regions of active regions AA
3
and AA
4
. Gate electrode interconnection line GA
3
is electrically coupled to a word line.
Each of gate electrode interconnection lines GA
1
and GA
2
has a region extending horizontally toward a central region. Gate electrode interconnection line GA
1
forms gate electrodes of MOS transistors PQ
1
and NQ
3
. Similarly, gate electrode interconnection line GA
2
forms gate electrodes of MOS transistors PQ
2
and NQ
4
, and gate electrode interconnection line GA
3
forms gate electrodes of MOS transistors NQ
3
and NQ
4
.
Local interconnection lines LI
1
to LI
7
are formed electrically coupling MOS transistors PQ
1
, PQ
2
, NQ
1
, NQ
2
, NQ
3
, and NQ
4
from one another. Local interconnection lines LI
1
to LI
7
are formed through a borderless process with respect to active regions AA
1
to AA
4
. Local interconnection lines LI
1
to LI
5
are formed above active regions AA
1
to AA
4
, and are electrically coupled directly to corresponding active regions AA
1
to AA
4
. Specifically, local interconnection line LI
1
electrically couples active regions AA
1
and AA
2
with each other. Similarly, local interconnection line LI
2
electrically couples active regions AA
1
and AA
3
with each other, and local interconnection line LI
3
electrically couples active regions AA
2
and AA
5
with each other.
Local interconnection line LI
2
corresponds to node ND
1
shown in
FIG. 51
, and local interconnection line LI
3
corresponds to node ND
2
shown in FIG.
51
. Local interconnection lines LI
1
to LI
7
are individually formed in self alignment with gate electrode interconnection lines GA
1
to GA
3
, and no contacts are formed in the portions in which local interconnection lines LI
2
and LI
3
overlap with gate electrode interconnection lines GA
1
and GA
2
. After the gate electrode interconnection lines are formed, the gate electrode interconnection lines are used as a mask, and the local interconnection lines are formed. In this process, the gate electrode interconnection lines are covered with an insulation film, and the contact holes are formed in portions for the contact with the local interconnection lines. Therefore, in the portions in which the gate electrode interconnection lines overlap with the local interconnection lines, the insulation film is formed on the gate electrode interconnection lines, and no contacts are formed for the local interconnection lines and the gate electrode interconnection lines.
Local interconnection line LI
2
is electrically coupled to gate electrode interconnection line GA
2
via a contact hole CH
1
. Similarly, local interconnection line LI
3
is electrically coupled to gate electrode interconnection line GA
1
via a contact hole CH
2
.
On the other hand, local interconnection line LI
4
is electrically coupled via a contact hole CH
3
to a first level metal interconnection line ML
1
formed vertically extending on an upper layer. Also, local interconnection line LI
5
is electrically coupled via a contact hole CH
4
to a first level metal interconnection line ML
4
formed on an upper layer thereof First level metal interconnection line ML
4
corresponds to memory cell ground line MVSS, and transfers ground voltage. Also, local interconnection lines LI
6
and LI
7
are electrically coupled via a contact hole CH
5
to a first level metal interconnection line ML
2
formed linearly extending in the vertical direction as viewed in the drawing. Also, local interconnection line LI
7
is electrically coupled via a conta

Affiliated with

Also associated with

Rating

Semiconductor memory device and testing method therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device and testing method therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and testing method therefor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3161811