Semiconductor memory device and test method thereof using...

Details Semiconductor memory device and test method thereof using... Semiconductor memory device and test method thereof using...

2002-09-26

2003-12-23

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S203000

Reexamination Certificate

active

06667919

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor device design, and more particularly, to a semiconductor memory device and method for testing the memory device using a row compression test mode.
2. Description of the Related Art
FIG. 1
is a block diagram showing a structure of a dynamic random access memory (hereinafter referred to as DRAM)
30
connected to a tester
20
. The DRAM
30
includes a control signal generation circuit
31
, a command decoder
32
, an address buffer
33
, a clock buffer
34
, a plurality of storage devices
40
and a data input/output circuit
39
. Each of the plurality of storage devices includes a memory array, a row decoder (RD), a column decoder (CD), and a sense amplifiers+input/output control circuit (SA+IO).
Control signal generation circuit
31
receives a variety of control signals such as /RAS, /CAS and /WE supplied from an external source, e.g., the external tester
20
, and generates and supplies a variety of internal control signals to command decoder
32
. Command decoder
32
decodes these internal control signals, generates a variety of command signals CMD
0
-CMDI and controls DRAM
30
as a whole by these command signals.
Address buffer
33
takes in address signals A
0
-Aj and supplies row address signals RA and column address signals CA to row decoders RDs and column decoder CDs, respectively. Clock buffer
34
receives a clock signal CLK supplied from an external source, generates and supplies to DRAM
30
as a whole an internal clock signal CLK′. DRAM
30
operates in synchronization with internal clock signal CLK′.
Row decoders RDs designate row addresses of memory arrays in response to row address signals RA supplied from address buffer
33
. Column decoders CDs designate column addresses of memory arrays in response to column address signals CA supplied from address buffer
33
.
Sense amplifiers+input/output control circuits SA+IO connect memory cells at addresses designated by row decoders RDs and column decoder CDs, respectively, to one ends of data input/output line pairs IOPs. Another ends of data input/output line pairs IOPs are connected to data input/output circuit
39
. Data input/output circuit
39
supplies data DQ
0
-k input from an external source to a selected memory cell via data input/output line pair IOP in a writing mode, and supplies as an output data DQ
0
-k read from a selected memory cell to an external device in a reading mode.
FIG. 2
is a more detailed block diagram of one of the plurality of storage devices
40
and
FIG. 3
is a schematic diagram of an individual column of the storage device shown in
FIG. 2
With reference to
FIGS. 2 and 3
, memory array
35
includes a plurality of memory cells MCs arranged in a matrix, word lines WLs arranged for respective rows, and bit line pairs BLs, /BLs (true bitlines/complement bitlines) arranged for respective columns. Each memory cell MC is located at a certain address designated by a row address RA and a column address CA. Each memory cell MC is of a well known type in the art and includes an N channel MOS transistor
50
for accessing, and a capacitor
51
for storing information. The word line WL transmits an output from row decoder
36
, and activates the memory cells MCs of the selected row. Bit line pair BL, /BL performs input/output of data to and from the selected memory cell MC.
Sense amplifier+input/output control circuit SA+IO
38
includes column select gates
41
s
, sense amplifiers
42
s
and equalizers
43
s arranged corresponding to respective columns. Column select gate
41
includes a pair of N channel MOS transistors
52
,
53
connected between bit line pair BL, /BL and data input/output line pair IO, /IO. A gate of each N channel MOS transistor is connected to column decoder
37
via a column select line CSL. When column select line CSL is activated by column decoder
37
to an “HI”(logical high) level which is a select level, the pair of N channel MOS transistors is rendered conductive coupling bit line pair BL, /BL and data input/output line pair IO, /IO.
Sense amplifier
42
amplifies a small potential difference between the bit line pair BL and /BL to a power supply voltage Vcc, in response to sense amplifier activating signals SE and /SE attaining “HI” and “L” levels, respectively.
Equalizer
43
includes an N channel MOS transistor
58
connected between bit lines BL and /BL, and N channel MOS transistors
59
and
60
connected between bit lines BL, /BL and a node N
1
, respectively. N channel MOS transistors
58
to
60
have their gates connected to node N
2
. Node N
2
receives a bit line equalizing signal BLEQ, and node N
1
receives a bit line potential Veql (=Vcc/2). Equalizer
43
equalizes the potentials of bit lines BL and /BL to bit line potential Veql in response to the bit line equalizing signal BLEQ attaining to the active level of “H” level. Here, signals SE, /SE, BLEQ are included in command signals CMDO-CMDi shown in FIG.
1
.
Next, an operation of DRAM
30
will be briefly described. In the writing mode, one of column decoders
37
activates column select line CSL in a column corresponding to column address signal CA to an activation level, that is an “H” level, rendering column select gate
41
conductive.
Data input/output circuit
39
supplies data to be written supplied from an external source to a bit line pair BL, /BL of the selected column via data input/output line pair IOP. Data to be written is given as a potential difference between bit line BL and complement bit line /BL. Then, one of row decoders
36
activates word line WL of a row corresponding to row address signal RA to an “H” level, that is the select level, rendering the row of N channel MOS transistors
51
of the memory cells MCs in the word line conductive. Electric charges of an amount corresponding to the potential of bit line BL or /BL is stored in the capacitor
51
of the selected memory cell MC.
In the reading mode, first, bit line equalization signal BLEQ is pulled down to an “L” level and the equalization of bit lines BL and /BL is stopped. One of row decoders
36
pulls up a word line WL of a row corresponding to row address signal RA to an “H” level that is the select level. The potentials of bit lines BL and /BL change by a minor amount according to the amount of electric charges in a capacitor
51
of an activated memory cell MC.
Then, sense amplifier activation signals SE and /SE attain an “H” level and “L” level, respectively and sense amplifier
42
is activated. When the potential of bit line BL is higher than the potential of complement bit line /BL by a minor amount, the potential of bit line BL is pulled up to an “H” level and the potential of complement bit line /BL is pulled down to an “L” level. Conversely, when the potential of bit line /BL is higher than the potential of bit line BL by a minor amount, the potential of complement bit line /BL is pulled up to an “H” level and the potential of bit line BL is pulled down to an “L” level.
One of column decoders
37
then activates column select line CSL of a column corresponding to column address signal CA to an “H” level rendering column select gate
41
of the column conductive. Data of bit line pair BL, /BL of the selected column is supplied to data input/output circuit
39
via column select gate
41
and data input/output line pair IO, /IO. Data input/output circuit
39
supplies read data to an external device, e.g., tester
20
.
To guarantee the quality of a DRAM, a variety of tests are performed before delivery. To test the memory cells in the DRAM array, a pattern of 1's and 0's is written into the array, and then it is read out by a cycle of normal read operations as described above. To test every cell, enough read operations must be performed to cover all addresses. However, this takes a considerable amount of time.
SUMMARY OF THE INVENTION
Accordingly, it is an aspect of the present invention to provide an equalizer testing circuit for a

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