Semiconductor memory device and test method thereof

Details Semiconductor memory device and test method thereof Semiconductor memory device and test method thereof

2011-05-10

2011-05-10

Mai, Son L (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S063000, C365S191000

Reexamination Certificate

active

07940587

ABSTRACT:
A semiconductor memory device comprises a memory cell array having memory cells arranged at intersections of word lines and bit lines, a first sense amplifier connected to a bit line at a predetermined position of the bit lines, a second sense amplifier connected to a bit line adjacent to the bit line at the predetermined position, a supplying circuit for supplying a predetermined voltage to each bit line connected to the first or second sense amplifier, and a sense amplifier control circuit capable of controlling the first and second sense amplifiers independently. In the semiconductor memory device, the sense amplifier control circuit performs a control in which an operation of either of the first and second sense amplifiers is stopped, the predetermined voltage is supplied to the bit line connected to the stopped sense amplifier, and the other of the first and second sense amplifiers is operated.

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