Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2007-06-12
2007-06-12
Dinh, Son (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S200000, C365S201000
Reexamination Certificate
active
11221721
ABSTRACT:
Disclosed is a semiconductor memory device, in which the refresh period of a fail cell or cells is set so as to be shorter than that of the normal cells, comprises a control circuit for exercising control in such a manner that, if, when refreshing the cell of a first address, generated responsive to a refresh command, with an input control signal being of a first value, a second address, differing as to the value of a predetermined bit from the first address, is determined to correspond to a fail cell, based on the information ore-programmed in a refresh redundant ROM, the cell of the second address is refreshed, and also in such a manner that, if, with the input control signal of a second value, the second address, differing as to the value of a predetermined bit from the first address, is determined to correspond to a fail cell, based on the predetermined information, only the cell of the second address is refreshed, without refreshing the cell of the first address, generated responsive to the refresh command.
REFERENCES:
patent: 6141278 (2000-10-01), Nagase
patent: 6590815 (2003-07-01), Mine
patent: 4-10297 (1992-01-01), None
Dinh Son
Elpida Memory Inc.
Nguyen Dang
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