Semiconductor memory device and signal line arrangement...

Details Semiconductor memory device and signal line arrangement... Semiconductor memory device and signal line arrangement...

2001-12-03

2003-02-18

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S190000

Reexamination Certificate

active

06522564

ABSTRACT:

CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 2001-6179, filed on Feb. 8, 2001, under 35 U.S.C. § 119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a signal line arrangement method thereof
2. Description of the Related Art
As semiconductor memory devices become highly highly integrated, efficient layout of the memory cells is required. A conventional semiconductor memory device includes a plurality of memory cell array blocks, a plurality of local data input/output line pairs connected to a plurality of the memory cell array blocks, multiple column selecting signal lines and a plurality of global data input/output line pairs arranged in the orthogonal direction with the plurality of local data input/output line pairs. As shown in
FIG. 1
, the column select signal lines CSL
1
, CSL
2
, . . . , CSLn and the plurality of global data input/output line pairs (GIO
1
and GIO
1
B) and (GIO
2
and GIO
2
B) are arranged in the same direction and are located adjacent to each other in the memory cell array. Typically each of the column select signal lines delivers a full swing signal, and the pair of global data input/output lines delivers smaller swing signals. A problem associated with such signal layout is the conflicting of the column select signal to the adjacent global data input/output lines due to coupling capacitance.
For example, the semiconductor memory device of
FIG. 1
includes memory cell array blocks such as BL
1
, BL
2
, BL
3
, and BL
4
, pairs of local data input/output lines such as (LIO
1
and LIO
1
B), (LIO
12
and LIO
12
B), (LIO
23
and LIO
23
B), (LIO
34
and LIO
34
B), and (LIO
4
and LIO
4
B), a word line WL, column selecting signal lines CSL
1
, CSL
2
, . . . , CSLn, and pairs of global data input/output lines such as (GIO
1
and GIO
1
B) and (GIO
2
and GIO
2
B). The word line WL is arranged along the direction of the pairs of local data input/output lines LIO
1
and LIO
1
B. The column select signal lines CSL
1
, CSL
2
, . . . , CSLn and pairs of global data input/output lines (GIO
1
and GIO
1
B) and (GIO
2
, and GIO
2
B) are arranged in a direction orthogonal to the pairs of local data input/output lines LIO
1
and LIO
1
B. Column selecting signal lines CSL
1
, CSL
2
, . . . , CSLn are arranged adjacent to pairs of global data input/output lines (GIO
1
and GIO
1
B) and (GIO
2
and GIO
2
B).
Referring to
FIG. 2
, which is a schematic diagram illustrating coupling capacitances between a column selecting signal line and global data input/output line pair in the conventional semiconductor memory device. The column selecting signal line CSL
1
and the global data input/output line pair GIO
1
and GIO
1
B are divided in three parts, and CA
1
, CB
1
, CC
1
, and CD
1
are coupling capacitances in the memory cell array block BL
1
, BL
2
, BL
3
, and BL
4
, respectively, between the column selecting signal line CSL
1
and the global data input/output line GIO
1
. CA
2
, CB
2
, CC
2
, and CD
2
are coupling capacitances in the memory cell array block BL
1
, BL
2
, BL
3
, and BL
4
, respectively, between the global data input/output line pair GIO
1
and GIO
1
B. CA
3
, CB
3
, CC
3
, and CD
3
are coupling capacitances in the memory cell array block BL
1
, BL
2
, BL
3
, and BL
4
, respectively, between the column selecting signal line CSL
1
and the inverting global data input/output line GIO
1
B.
When the column selecting signal line CSL
1
is enabled or disabled, the sum of coupling capacitances, CA
1
+CB
1
+CC
1
+CD
1
, couples the signal of the CSL
1
line and affects a signal in the global data input/output line GIO
1
. If the coupling is severe, the signal of the global data input/output line GIO
1
can change according to the signal change of the column selecting signal line CSL
1
.
In the same way, when the column selecting signal line CSL
1
is enabled and/or disabled, the signal of the inverting global data input/output line GIO
1
B can change according to the signal change of the column selecting signal line CSL
1
. However, the inverting global data input/output line GIO
1
B is located farther than the global data input/output line GIO
1
from the column selecting signal line CSL
1
, the effect of CSL
1
on the inverting global data input/output line GIO
1
B is less than the signal of the global data input/output line GIO
1
.
Referring to
FIG. 3
, which is an operation-timing diagram of the memory cell array block BL
1
of
FIG. 1
, and more particularly illustrating a case that an inverting write enable signal WEB of “high” logic level is applied and data of “low” logic level is read from pairs of bit lines BLP
1
and BLP
2
.
A row address X is inputted in response to a row address strobe signal RASB of “low” logic level, and a column address Y is inputted in response to a column address strobe signal CASB of “low” logic level. By decoding the row address X, a word line enable signal WL of “high” logic level is generated, and also block selecting signals BLS
1
and BLS
12
of “high” logic level are generated. By decoding the column address Y, a control signal of “high” logic level in the column selecting signal line CSL
1
is generated. In addition, the precharge signal PRE of “low” logic level is generated before the word line enable signal WL of “high” logic level is generated. In response to the precharge signal PRE of “low” logic level, pairs of bit lines BLP
1
and BLP
2
, pairs of local data input/output lines LIO
1
, LIO
1
B, LIO
2
, and LIO
2
B, and pairs of global data input/output lines (GIO
1
and GIO
1
B) and (GIO
2
and GIO
2
B) are precharged.
When the word line enable signal WL of “high” logic level starts to generate, each pair of bit lines BLP
1
and BLP
2
begins to develop toward “high” logic level and “low” logic level, respectively.
When the control signal of “high” logic level in the column selecting signal line CSL
1
of is generated, data of pairs of bit lines BLP
1
and BLP
2
are transmitted to pairs of local data input/output lines (LIO
1
and LIO
1
B) and (LIO
12
and LIO
12
B). In response to block selecting signals BLS
1
and BLS
2
, data in pairs of local data input/output lines (LIO
1
and LIO
1
B) and (LIO
12
and LIO
12
B) are transmitted to corresponding pairs of global data input/output lines (GIO
1
and GIO
1
B) and (GIO
2
and GIO
2
B), and are amplified by input/output sense amplifiers.
When data in each pair of global data input/output lines (GIO
1
and GIO
1
B) and (GIO
2
and GIO
2
B) start to develop toward “high” logic level and “low” logic level, the input/output sense amplifiers detect a voltage difference of the data transmitted to pairs of global data input/output lines (GIO
1
and GIO
1
B) and (GIO
2
and GIO
2
B), and then amplify the voltage difference. Therefore, the faster the starting time developing toward “high” logic level and “low” logic level in data transmission to pairs of global data input/output lines (GIO
1
and GIO
1
B) and (GIO
2
and GIO
2
B), the faster the data read access time.
However, the conventional semiconductor memory device arranges the column selecting signal line CSL
1
and the global data input/output line GIO
1
adjacently as shown in FIG.
2
. Therefore, the coupling capacitances between the column selecting signal line CSL
1
and the global data input/output line GIO
1
affect data transmitting to a pair of global data input/output lines GIO
1
and GIO
1
B. In other words, a full swing to “high” logic level in the column selecting signal line CSL
1
increases a voltage of a &Dgr;V
1
level in the global data input/output line GIO
1
. A transition to “low” logic level in the column selecting signal line CSL
1
lowers a voltage of a &Dgr;V
1
level in the global data input/output line GIO
1
. On the other hand, the voltage of the inverting global data input/output line GIO
1
B is increased slightly.
In other words, when a signal in the column selecting signal lin

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