Semiconductor memory device and semiconductor device

Details Semiconductor memory device and semiconductor device Semiconductor memory device and semiconductor device

1996-02-16

1998-01-13

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Including signal clamping

365226, G11C 514

Patent

active

057086109

ABSTRACT:
For each of pads for control clock signals and address signals included in a DRAM, an n type well region is provided, and each n type well region is connected to an upper power supply means only by means of a first lower power supply line. Therefore, compared with the conventional device in which n type wells are connected to each other by a second lower power supply line, current flowing from the resistance element in a p type well to the upper power supply line is reduced. Therefore, damage to the resistance element 8 can be prevented, and surge immunity of the DRAM is increased.

REFERENCES:
patent: 4720737 (1988-01-01), Shirato
patent: 5072271 (1991-12-01), Shimizu et al.
patent: 5235201 (1993-08-01), Honna
patent: 5349227 (1994-09-01), Murayama
patent: 5581103 (1996-12-01), Mizukami

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