Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-09-28
2001-05-15
Wright, Norman Michael (Department: 2131)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S035000, C707S793000, C705S016000
Reexamination Certificate
active
06233698
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as a memory card which is capable of writing data and uses a nonvolatile semiconductor memory, and to a sales processor such as an electronic cash register and a POS (point of sale) terminal having the semiconductor memory device for storing sales data.
2. Description of the Related Art
Electrically writable and nonvolatile EPROMs and flash memories have been conventionally used in semiconductor memory devices such as memory cards. EPROMs and flash memories are nonvolatile semiconductor memories in which stored data is maintained even after power supply is stopped. These memories are widely used because of their comparatively large capacities and high data reading speeds. Once data is normally written in a nonvolatile semiconductor memory, the written data is surely maintained until the data is erased. Erasing the storage contents from a nonvolatile semiconductor memory requires control or a voltage that is different from control or a voltage required in the normal operation state, and the storage contents never change in the normal operation state. Thus, nonvolatile semiconductor memories are highly reliable. For this reason, nonvolatile semiconductor memories have been preferably used for storing sales data of electronic cash registers and POS (point of sale) terminals handling cash. For example, Japanese Unexamined Patent Publication JP-A 5-46490 (1993) discloses to use a memory card device using an electrically erasable and writable EEPROM for storing image data in an electronic still camera apparatus.
Since nonvolatile semiconductor memories surely maintain the data normally written therein, data writing into nonvolatile semiconductor memories is not easy. For this reason, there is a possibility that a writing error occurs in data writing and data writing cannot be performed normally. Whether writing is performed normally or not can be determined by collating the written data with the data to be written. When there is a difference between the data, the difference is detected as an error. In JP-A-5-46490, for an EEPROM having its memory space partitioned into a plurality of pages, the presence or absence of an error is detected for each page, and with a specific page as an error flag area, an error flag representative of the presence or absence of an error in each page is recorded in the error flag area. The data written in an error occurring page is newly written in an alterantive blank page, and the data written in the error occurring page are replaced by address data all representative of an address of the alternative page. When the data is read out, the error occurring page is determined by referring to the error flag area, the address data is read out from the whole of the error occurring page to determine the address of the alternate page by majority, and based on the determined address, the data is read out from the alternative page.
In JP-A-5-46490, since the address of the alternative page corresponding to the error occurring page is determined by majority from a multiplicity of addresses written in the error occurring page, it is necessary for the controller for controlling writing into the semiconductor memory to control writing of the address into the error occurring page after the address of the alternative page is determined. This complicates the function of the controller and increases the writing time at the time of occurrence of an error in accordance with the time necessary for writing the address of the alternative page. Since the possibility is strong that a page of a nonvolatile semiconductor memory in which an error occurs includes a memory cell being prone to result in an error, in order to surely determine the address of the alternative page by majority, it is necessary that the data amount for one page be large and the number of addresses of the alternative page written in the error occurring page be great. Since it is necessary to read a multiplicity of data and determine the address of the alternative page by majority when the address of the alternative page is read in, the data retrieval performed later is difficult and the data reading speed is low.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device capable of easily writing and reading data at high speed regardless of whether an error occurs or not, and a sales processor provided with the same.
In a first aspect of the invention, there is provided a semiconductor memory device using a writable nonvolatile semiconductor memory, the semiconductor memory having first and second memory areas each divided into data records on a prescribed byte number basis, and as well a flag area for writing a writing state as a flag, the semiconductor memory device comprising:
writing error detecting means for judging whether data writing is normally carried out or not during writing data;
flag writing means for writing a writing state as a flag in response to a detection result of the writing error detecting means; and
writing switching means for successively writing data to be stored into a data record of the first memory area and when the writing error detecting means detects a writing error, newly writing the data into a data record of the second memory area.
According to the first aspect of the invention, since the writing switching means successively writes data to be recorded into the first memory area of the semiconductor memory, data reading processing can be effectively performed, so that the data reading speed can be increased. When the writing error detecting means detects a writing error when the writing switching means writes data into a data record of the first memory area, the flag writing means writes the error into a flag area and the writing switching means newly writes into a data record of the second memory area the data in which the writing error is detected, so that the data to be stored is surely stored.
As described above, according to the first aspect of the invention, since the data written by the writing switching means are successively written into data records of the first memory area, data having no writing error can be effectively read out at high speed. The presence or absence of a writing error can be easily determined by referring to the flag area. Since data having a writing error is written in the second memory area, data can be surely read out by reading out data from data records of the second memory area.
In a second aspect of the invention, the semiconductor memory device further comprises readout switching means for successively reading out data from the data records of the first memory area with reference to the flag area and when a flag representative of a writing error is written, performing switching so that data is read out from the data records of the second memory area.
According to the second aspect of the invention, since the readout switching means successively reads out data from the data records of the first memory area with reference to the flag area, data reading can be performed at high speed when a flag representative of a writing error is not written. When the flag representative of a writing error is written, switching is performed so that data is read out from the data records of the second memory area, so that the data stored in the semiconductor memory can be surely read out. As described above, according to the second aspect of the invention, from the semiconductor memory device, data can be surely read out at high speed. Moreover, the readout switching means may be added to the semiconductor memory device of the second aspect of the invention.
In a third aspect of the invention, the writing switching means performs writing successively from the forefront address of the second memory area when a writing error is detected.
According to the third aspect of the invention, since the data writing into the second memory area performed by the writing switching means when a writing err
Conlin David G.
Dike Bronstein, Roberts & Cushman LLP
Sharp Kabushiki Kaisha
Wright Norman Michael
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