Semiconductor memory device and refreshing method of...

Details Semiconductor memory device and refreshing method of... Semiconductor memory device and refreshing method of...

2001-05-22

2002-12-03

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S236000, C365S230010

Reexamination Certificate

active

06490215

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device having a plurality of banks, and, more particularly, to a semiconductor memory device which performs write and read operations on a selected bank and a refresh operation on non-selected banks in parallel.
The recent achievement of larger capacity and a greater number of bits demands the use of DRAMs each of which has a plurality of banks mounted on a same semiconductor substrate and performs write and read operations on a selected bank and a refresh operation on non-selected banks in parallel.
FIG. 1
is a schematic block diagram of a synchronous DRAM (SDRAM)
100
according to the prior art. The SDRAM
100
includes a plurality of banks MB
0
to MBn mounted on a semiconductor substrate. The SDRAM
100
is independently accessable by the individual banks, so that each bank operates as an independent DRAM.
Each of the banks MB
0
-MBn includes a memory cell array having a plurality of memory cells, a memory cell select circuit which selects memory cells in accordance with an address signal, a data write circuit which writes cell information in selected memory cells and a data read circuit which reads cell information from selected memory cells.
The SDRAM
100
further includes refresh address counters RC
0
to RCn corresponding to the banks MB
0
-MBn and a switch circuit SW
1
connected between the refresh address counters RC
0
-RCn and the banks MB
0
-MBn. Every time the refresh address counters RC
0
-RCn receive a refresh request signal RQ, they generate refresh address signals RA
00
to RA
09
, RA
10
to RA
19
, and RAn
0
to RAn
9
of, for example, 10 bits corresponding to the banks MB
0
-MBn, through a count-up operation, and provide the refresh address signals to the switch circuit SW
1
.
The switch circuit SW
1
receives external address signals EA
0
to EA
9
and bank control signals BC
0
to BCn from external circuits and supplies address signals A
00
to A
09
, A
10
to A
19
, and An
0
to An
9
to the respective banks MB
0
-MBn via ten respective signal lines. The external address signals EA
0
-EA
9
are used to perform a write operation or read operation with respect to the banks MB
0
-MBn. The bank control signals BC
0
-BCn are used to select any bank on which a write operation or read operation is to be performed.
The switch circuit SW
1
selects, for example, the address signals A
00
-A
09
provided to the bank MB
0
from the external address signals EA
0
-EA
9
and the refresh address signals RA
00
-RA
09
. Likewise, the switch circuit SW
1
selects the address signals A
10
-A
19
provided to the bank MB
1
from the external address signals EA
0
-EA
9
and the refresh address signals RA
10
-RA
19
. Further, the switch circuit SW
1
selects the address signals An
0
-An
9
provided to the bank MBn from the external address signals EA
0
-EA
9
and the refresh address signals RAn
0
-RAn
9
.
The operation of the SDRAM
100
will be discussed referring to FIG.
2
. The individual banks MB
0
-MBn operate in synchrony with an external clock signal CLK. When an active signal ACTV is provided to the bank MB
0
at a first timing t
1
and the bank control signal BC
0
is provided to the switch circuit SW
1
, for example, the switch circuit SW
1
selects the external address signals EA
0
-EA
9
and provides the selected external address signals (address signals A
00
-A
09
) to the bank MB
0
. The bank MB
0
is enabled by the active signal ACTV and executes a write operation or a read operation in accordance with the external address signals EA
0
-EA
9
.
At the same time, the refresh request signal RQ is provided to each of the refresh address counters RC
0
-RCn. Each of the refresh address counters RC
0
-RCn performs the count-up operation and provides a refresh address signal to the switch circuit SW
1
.
The switch circuit SW
1
provides refresh address signals (address signals A
10
-A
19
, An
0
-An
9
) to the non-selected banks MB
1
-MBn to perform a refresh operation of the cell information.
When the active signal ACTV is provided to the bank MB
1
at a second time t
2
and the bank control signal BC
1
is provided to the switch circuit SW
1
, the switch circuit SW
1
provides the external address signals EA
0
-EA
9
(address signals A
10
-A
19
) to the bank MB
1
. The bank MB
1
is enabled by the active signal ACTV and performs a write operation or a read operation in accordance with the external address signals EA
0
-EA
9
.
At the same time, the switch circuit SW
1
respectively provides refresh address signals to the non-selected banks MB
0
and MB
2
-MBn to refresh cell information. Thereafter, such a write operation or a read operation and refresh operation are repeated.
When a self-refresh command is provided to the individual banks MB
0
-MBn, the refresh request signal RQ which is generated within the chip is provided to the individual refresh address counters RC
0
-RCn. Then, the refresh address signals provided from the refresh address counters RC
0
-RCn are provided to the respective banks MB
0
-MBn via the switch circuit SW
1
, and all of the banks MB
0
-MBn perform a refresh operation simultaneously.
The SDRAM
100
requires that the same number of address signal lines as the number of bits of the address signals should be laid between the switch circuit SW
1
and the banks MB
0
-MBn. As the number of banks increases, therefore, the number of address signal lines increases. This results in an inevitable increase in the layout area for the address signal lines, thus increasing the area of the SDRAM
100
.
Since the write operation or read operation of a selected bank and the refresh operation of non-selected banks are executed simultaneously, the peak of the consumed current of the entire device is relatively high.
When a self-refresh command is provided to each of the banks MB
0
-MBn, all of the banks perform the refresh operation simultaneously. The peak of the operational current in this case is relatively high. To supply the current in a stable manner, even at the time of such a peak, the power lines should have a relatively wide width. This also increases the area of the SDRAM
100
.
No refresh operation is needed for any bank that has just finished a write operation or a read operation in accordance with the external address signals EA
0
-EA
9
. However, a bank that just finished a write operation or a read operation together with the other non-selected banks actually do undergo a refresh operation. This means that the bank consumes a wasteful current. In other words, the overall consumed current of the SDRAM
100
increases.
SUMMARY OF THE INVENTION
Accordingly, it is a first object of the present invention to provide a semiconductor memory device that suppresses an increase in the circuit area which is originated from the layout of address signal lines.
It is a second object of the invention to provide a semiconductor memory device which suppresses the peak of the operational current of each bank, thus reducing the overall consumed current.
In one aspect of the present invention, there is provided a semiconductor memory device including a plurality of banks, a plurality of refresh address counters, a switch circuit, and a plurality of address holding circuits. Each of the plurality of banks performs a write operation and read operation according to an external address signal and a refresh operation according to a refresh address signal. The plurality of refresh address counters generate a plurality of refresh address signals associated with the plurality of banks in response to a refresh request signal. The switch circuit is connected to the plurality of refresh address counters and selectively outputs the external address signal and a refresh address signal generated by one of the plurality of refresh address counters in accordance with the refresh request signal. Each of the plurality of address holding circuits is connected between the switch circuit and the plurality of banks, holds one of the refresh address signals and the external address signal outputs fro

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