Semiconductor memory device and refresh period controlling...

Details Semiconductor memory device and refresh period controlling... Semiconductor memory device and refresh period controlling...

2005-06-15

2009-02-17

Torres, Joseph D (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C714S754000

Reexamination Certificate

active

07493531

ABSTRACT:
Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors.

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Patent Abstract, TW 00550567, Sep. 2003, 1 pg.
Patent Abstract, TW 00548648, Aug. 2003, 1 pg.
Y. Katayama et al., Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention, 1999 International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 311-318.

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