Semiconductor memory device and refresh control circuit

Details Semiconductor memory device and refresh control circuit Semiconductor memory device and refresh control circuit

2003-06-11

2004-11-02

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233500

Reexamination Certificate

active

06813212

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor memory device and a refresh control circuit, and more particularly to a semiconductor memory device, wherein a memory cell array comprises the same memory cells as DRAM (dynamic random access memory), and the semiconductor memory device is operable in the same specification as SRAM (static random access memory), and the semiconductor memory device is compatible to SRAM, where a write enable signal, which decides a timing of writing to a memory cell, is non-synchronously given to a write address, and a refresh control circuit for controlling a refresh operation.
BACKGROUND ART
SRAM and DRAM are most typical ones of semiconductor memory devices which accept random accesses. As compared to DRAM, in general, SRAM exhibits a high speed operation. Further, supplying a power to SRAM and entry of an address into the same are sufficient for enabling SRAM to detect any address transition and cause an internal sequencer circuit to operate for performing read and write operations. SRAM may be operable based on input signals with more simple waveforms as compared to DRAM. This allows simplifying a configuration of a circuit which generates the input signal with such the waveform.
SRAM does not need refresh operation, which is needed for DRAM to hold data in the memory cells in DRAM, for which reason managing SRAM is easier. SRAM is advantageous in that a small current is needed for holding data in a stand-by state due to no need for the refresh operation. For those reasons, SRAM has widely been used in a variety of application. In general, SRAM, however, needs six transistors for one memory cell, for which reason a chip of SRAM is larger in size than DRAM, and thus SRAM is higher in price than DRAM.
Meanwhile, DRAM is supplied with a row address and a column address separately or at different two timings, wherein there are needed RAS (row address strobe) and CAS (column address strobe) which define separate timings of capturing the row address and the column address, respectively. Further, a control circuit is needed for cyclically refreshing memory cells. DRAM is more complicated than SRAM in view of timing controls.
DRAM also has a problem with a larger current consumption due to the need for refreshing memory cells even when no external access is made. Notwithstanding, the memory cell of the DRAM may comprise a single capacitor and a single transistor. This makes it relatively easy to achieve a large memory capacity with a small chip size. DRAM is more cheaper than SRAM, provided that the required memory capacity is the same.
SRAM is the main-stream of the semiconductor memory device which is utilized in a portable device, typically, a portable telephone device. This reason is as follows. The past portable telephone device does not need a semiconductor memory device with a large capacity because the past portable telephone device has simple functions. SRAM is more simple in timing control operation than DRAM. SRAM has a smaller current consumption in the stand-by state, for which reason SRAM is more suitable for the portable telephone device which is needed to prolong a continuous communication time and a continuous stand-by time as many as possible.
Recently, however, an advanced portable telephone device has a variety of function, for example, a function of transmitting and receiving e-mails, and another function of making an access to a variety of site for obtaining informations about restaurants. A very recent portable telephone device is also incorporated with a function of making an access to a Web-server on the Internet and displaying summarized contents of a home page. In the future, the portable telephone device may be expected to make accesses to home pages on the Internet similarly to the present desk top type personal computer.
In order to realize those functions, a simple display in text format by the conventional portable telephone device is insufficient but a graphic display for providing a variety of multi-media information to users is essential. It is necessary for this purpose that a large mount of data received from a public network is temporarily stored in the semiconductor memory device in the portable telephone device. It is essential that the semiconductor memory device integrated in the portable device has a large capacity such as DRAM. It is absolute that the portable device has a small size and a light-weight, for which reason it is necessary that the capacity of the semiconductor memory device is increased without increasing the size and the weight.
As described above, SRAM is preferable in view of easy operation and power consumption of the semiconductor memory device integrated in the portable device. DRAM is preferable in view of large capacity. Namely, a semiconductor memory device taking both advantages of SRAM and DRAM is optimum for those portable devices. A semiconductor memory device of this kind so called as “pseudo SRAM” has already been considered, wherein the same memory cells are used as those of DRAM, while the specification is almost the same as that used for DRAM in an external view.
The pseudo SRAM does not need to perform such a separate supply of a row address and a column address as conducted in DRAM, for which reason the pseudo SRAM does not need timings signals such as RAS and CAS. The pseudo SRAM may perform a batch-supply of addresses similarly to the general-purpose SRAM. The pseudo SRAM takes the addresses therein by triggering a chip enable signal for read/write operations, wherein the chip enable signal corresponds to a clock of a semiconductor memory device operable synchronizing with the clock signal.
The pseudo SRAM is not necessarily complete-compatible to the general-purpose SRAM. The majority of the pseudo SRAM is provided with refresh control terminals for externally controlling refreshes of memory cells. The external control to the refresh of the pseudo SRAM is needed. The majority of the pseudo SRAM is not easy in operation as compared to SRAM, and needs an additional circuit for refresh control. Another pseudo SRAM has been proposed which is operable in the completely similar specification to the general-purpose SRAM, without external control to the refresh of the pseudo SRAM. This pseudo SRAM also has the following disadvantages.
For writing data into the general-purpose SRAM, generally, an access address is designated as an external address, and subsequently, a write enable signal is activated to give a write instruction. Data to be written are supplied, and input data into SRAM are commenced to be captured, before the input data are defined synchronizing with a rising or a falling of a signal which inactivates the write enable signal.
One of the specifications needed for use of the general-purpose SRAM is an address hold time (Twr). The address hold time Twr defines a time duration, in which the external address presenting the access address has to be held at the same value after the write enable signal has been inactivated. Normally, the general-purpose SRAM may be configured to define zero second as the minimum value of the address hold time Twr.
The conventional pseudo SRAM performs the control to the refresh operation without sufficient consideration of a relationship between a timing of transition of the write enable signal and another timing of transition of the external address signal. For this reasons, immediately after the data write operation (the inactivation of the write enable signal) has been completed, the refresh operation may be commenced. In this case, it is possible that the external access address overlaps an internally generated refresh address.
This point is particularly remarkable problem in such a configuration that any transition of the address signal is detected for the refresh operation. One countermeasure may be considered that the external address is so defined to remain for a period of time after the write enable signal has been inactivated. In this case, however, the address hold time Twr is defined, for example, in a few n

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