Semiconductor memory device and redundant output switch thereof

Details Semiconductor memory device and redundant output switch thereof Semiconductor memory device and redundant output switch thereof

2002-03-27

2003-11-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700, C365S230030

Reexamination Certificate

active

06643197

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor memory devices and, in particular, to redundant output switches for use in a semiconductor memory device.
BACKGROUND OF THE INVENTION
Many of today's semiconductor memory devices include redundant elements that are available to replace malfunctioning or defective elements. By including redundant elements on memory devices, the overall yield of marnfacture can be increased and improved. Therefore, the use of redundant elements on a memory chip to replace defective elements can result in lower capital manufacturing costs and earlier introduction of new products on existing wafer fab lines or in new process technologies.
As illustrated in
FIG. 1
, a conventional semiconductor memory device includes an ordinary memory cell array
11
, an ordinary decoder
12
, a redundant switch circuit
13
and a redundant memory cell array
14
. Typically, the ordinary memory cell array
11
has a plurality of ordinary memory cells
11
(m,n) arranged in an M-column-by-N-row structure, where 1≦m≦M, 1≦n≦N and M, N are a first and a second positive integers greater than one. That is, the ordinary memory cell array
11
includes M columns, and each column has N ordinary memory cells. In other words, the ordinary memory cell array
11
includes N rows, and each row has M ordinary memory cells.
The memory cell array
11
also comprises 1st through Mth bit lines or ordinary columns
11
B-
1
to
11
B-M, and 1st through Nth word lines
11
W-
1
to
11
W-N. Arn ordinary memory cell refers to
11
(m,n) that is connected to the mth bit line
11
B-m and the nth word line
11
W-n. As depicted in
FIG. 1
, the ordinary memory cell array
11
is coupled to a data bus
102
. The ordinary memory cell array
11
is also connected to the ordinary decoder
12
. The decoder
12
receives an address signal and its complement from an address bus
101
. When a decode-inhibit signal
106
is de-asserted, the ordinary decoder
12
decodes the received pair of complementary address signals to generate a column and a row decode signals
104
C,
104
R and to provide them to the ordinary memory cell array
11
.
The ordinary decoder
12
includes a row decoder
12
R and a column decoder
12
C. The row decoder
12
R receives a row address and its complement. The decoder
12
R decodes the pair of complementary row addresses to generate the row decode signal
104
R. In similar fashion, the column decoder
12
C receives a column address and its complement. The decoder
12
C decodes the pair of complementary column addresses to generate the column decode signal
104
C. The row decode signal
104
R is provided for driving one of the N word lines. Lkewise, the column decode signal
104
C is provided for driving one of the M bit lines.
Still referring to
FIG. 1
, the redundant memory cell array
14
has a plurality of redundant memory cells
14
(p,n) arranged in a P-column-by-N-row structure, where 1≦p≦P, 1≦n≦N and P is a third positive integer greater than one. That is, the redundant memory cell array
14
includes P columns, and each column has N redundant memory cells. In other words, the redundant memory cell array
14
includes N rows, and each row has P redundant memory cells.
The redundant memory cell array
14
also comprises 1st through Pth bit lines or redundant columns
14
B-
1
to
14
B-P, and 1st through Nth word lines
14
W-
1
to
14
W-N. A redundant memory cell refers to
14
(p,n) that is connected to the pth bit line
14
B-p and the nth word line
14
W-n. The redundant switch circuit
13
is coupled between the redundant memory cell array
14
and the data bus
102
as shown in FIG.
1
.
The semiconductor memory device is tested shortly after it is manufactured to find and identify ordinary columns that contain defective ordinary memory cells. If one or more defective columns are identified, they are replaced with redundant columns of the redundant memory cell array
14
such that the memory device having defective cells is still an acceptable product.
A defective column address for the ordinary memory cell array
11
is set by cutting isolation elements, such as fuses, in a redundant decoder
15
. When a defective column is addressed, the redundant decoder
15
and the redundant switch circuit
13
operate in a manner that is transparent to the external circuitry thereby routing all data transactions to the corresponding redundant column instead of the defective column in the ordinary memory cell array
11
.
Referring to
FIG. 2
, the redundant decoder
15
includes P redundant decode circuits
15
-
1
~
15
-P that are each connected to a corresponding redundant column in the redundant memory cell array
14
. As an illustrated example, the third positive integer P is equal to 2. Hence, the redundant decoder
15
has redundant decode circuits
15
-
1
and
15
-
2
. Since the redundant decode circuits
15
-
1
and
15
-
2
are constructed and operate in a similar fashion, the detailed schematic diagram of the redundant decode circuit
15
-
2
is omitted in FIG.
2
.
For illustration, the memory device described herein provides an 8-bit column address [X
1
T:X
8
T] and an 8-bit complementary column address [X
1
N:X
8
N]. Typically, a semiconductor memory device provides Q-bit column address and Q-bit complementary column address separately, where Q is a fourth positive integer greater than one. As depicted, the redundant decode circuit
15
-
1
includes sixteen NMOS transistors
20
1
~
20
16
, a PMOS transistor
21
, sixteen fuses
22
1
~
22
16
, and an AND gate
206
.
The PMOS transistor
21
has its source connected to a high voltage source, its drain connected to a common node
201
, and its gate connected to a control circuit (not shown) to receive a control signal
103
a.
The fuses
22
1
~
22
16
are coupled between each of the NMOS transistors
20
1
~
20
16
and the common node
201
. Each NMOS transistor (
20
1
~
20
16
) has its source connected to ground or a low voltage source, and its drain connected to the corresponding fuse (
22
1
~
22
16
) The odd numbered NMOS transistors
20
1
,
20
3
, . . . ,
20
15
have their gates receive the 8-bit column address [X
1
T:X
8
T] of the address signal; the even numbered NMOS transistors
20
2
,
20
4
, . . . ,
20
16
have their gates receive the 8-bit complementary column address [X
1
N;X
8
N] of the address signal.
One input terminal of the AND gate
206
is connected to the conmon node
201
, the other input terminal of the AND gate
206
is connected to the control circuit (not shown) to receive a control signal
103
b.
The AND gate
206
generates a redundant decode signal
105
-
1
and provides it to the 1st redundant column in the redundant memory cell array
14
in FIG.
1
. In similar fashion, the redundant decode circuit
15
-
2
receives the column address [X
1
T:X
8
T] and its complement [X
1
N:X
8
N], and the control signals
103
a~b. Therefore, the redundant decode circuit
15
-
2
generates a redundant decode signal
105
-
2
and provides it to the 2nd redundant column in the redundant memory cell array
14
in FIG.
1
. The redundant decoder
15
further includes an OR gate
203
receiving the redundant decode signals
105
-
1
and
105
-
2
. The OR gate asserts the decode-inhibit signal
106
when the redundant decode signal
105
-
1
or
105
-
2
is activated.
Referring now to
FIG. 3
, the redundant switch circuit
13
comprises output set circuits
130
-
1
and
130
-
2
respectively receiving the redundant decode signals
105
-
1
and
105
-
2
. Each output set circuit outputs a select code S-
1
/S-
2
according to its internal setting. As illustrated in
FIG. 4
, each of the output set circuits
130
-
1
and
130
-
2
is constructed of PMOS transistors and fuses f-
1
~f-M (M=8, for example). By selectively cutting the fuses f-
1
~f-
8
, the pth output set circuit generates output signals [op
1
:op
8
] to form the select code S-p. For instance, each output s

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