Semiconductor memory device and redundancy method thereof

Details Semiconductor memory device and redundancy method thereof Semiconductor memory device and redundancy method thereof

2000-11-20

2003-07-08

Lebentritt, Michael S. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S222000, C365S230030, C365S230060, C365S230080, C365S189110

Reexamination Certificate

active

06590814

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, a semiconductor memory device using a redundancy method that can substitute a data input/output line pair with an adjacent data input/output line pair.
2. Description of the Prior Art
A semiconductor memory device of merged memory logic (MML) typically has a large number of data input/output pins for high-speed input/output of a large quantity of data. The semiconductor memory device conventionally has a signal line arrangement in which word lines are perpendicular to bit lines, column select signal lines are parallel to the word lines, and data input/output lines are parallel to the bit lines. Such semiconductor memory devices further include redundancy circuitry capable of substituting a redundant data input/output line for a data input/output line connected to a defective memory cell. U.S. Pat. No. 5,892,719, for example, describes a redundancy method that substitutes a redundant data input/output line for a data input/output line connected to a defective memory cell. A redundancy method disclosed in U.S. Pat. No. 5,796,662 replaces a data input/output line connected to a defective memory cell with an adjacent redundant data input/output line.
FIG. 1
is a block diagram of a redundancy circuit of a semiconductor memory device disclosed in U.S. Pat. No. 5,796,662. The memory device includes n memory cell array blocks
10
-
1
to
10
-n, n fuse circuits
12
-
1
to
12
-n, buffers
14
-
1
and
14
-
2
, and shift circuits
16
-
1
and
16
-
2
.
Output signals of n fuse circuits
12
-
1
to
12
-n program redundancy decoders and shift select signals of each of n memory cell array blocks
10
-
1
to
10
-n. If a memory cell array block
10
-(n/2+1) is selected, a fuse circuit
12
-(n/2+1) transmits bit shift select signals to a buffer
14
-
2
. The buffer
14
-
2
transmits shifting control signals to a shift circuit
16
-
2
, and the shift circuit
16
-
2
shifts a data input/output line pair in response to the shifting control signals.
A redundancy circuit of a semiconductor memory device shown in
FIG. 1
includes fuse circuits that are programmable to indicate whether addresses of respective memory cell array blocks are defective addresses. The redundancy method of the semiconductor memory device of
FIG. 1
can handle multiple defective memory cell array blocks in one bank. But, for a memory cell array bank constructed in multiple banks, it is difficult to dynamically generate a shifting control signal according to a column cycle. That is, the prior redundancy method has difficulty in generating the shifting control signal dynamically to the column cycle in the active state of multiple banks when different blocks of different banks have different defective addresses.
That is, it is possible to generate the shifting control signal dynamically to column cycle for one bank, but it is difficult to generate different defective addresses of different blocks of different banks dynamically to column cycle in the active state of multiple banks in a multi-bank structure.
To solve the above problem, every data input/output line pair can have a fuse corresponding to each of memory cell array blocks, and the redundancy method cuts the fuses behind a defective data input/output line pair by each block after a pre-laser test. This method needs a large number of fuses by memory cell array blocks. For example, a device having 512 data input/output lines and eight memory cell array blocks requires 4096 fuses to store defective addresses separately by the eight memory cell array blocks and to generate input/output shift information dynamically. Typically, the large number of fuses makes this method impractical. Also, the fuses make it difficult to layout power lines or signal lines.
SUMMARY OF THE INVENTION
Some embodiments of the present invention provide a semiconductor memory device that can generate a shifting control signal dynamically to a column cycle in a multi-bank structure without requiring the large number of fuses used in known memory devices.
Other embodiments of the present invention provide a redundancy method that can generate a shifting control signal dynamically to a column cycle in a multi-bank structure without requiring the large number of fuses used in known memory devices.
One exemplary embodiment of a semiconductor memory device in accordance with the present invention includes an address setting means to set a redundant control signal and a defective address respectively in response to each of a plurality of first control signals, and a plurality of decoders and shifting control circuits for generating the decoding output signals by decoding each redundant control signal and defective address, latching a plurality of decoding output signals in response to each of a plurality of second control signals, and generating the latched data with a plurality of shifting control signals in response to each of the plurality of third control signals.
In one preferred embodiment, the present invention includes a plurality of memory cell array banks, a plurality of memory cell array blocks of each of the plurality of memory cell array banks, and a plurality of partial blocks of each of the memory cell array blocks connected to each of a plurality of data input/output line pairs and a predetermined number of redundant partial blocks of each of the memory cell array blocks connected to each of a predetermined number of redundant data input/output line pairs, includes an address setting means for setting a redundant control signal and defective addresses of each of the memory cell array blocks, a plurality of decoders and shifting control signals generation means for generating a plurality of shifting control signal for controlling shifting of the data input/output line pairs and of a predetermined number of redundant data input/output line pairs by decoding the redundant control signal and the defective address, and a plurality of switching means for outputting data output from a data input/output line pair adjacent to a corresponding data input/output line pairs in response to each of the shifting control signals, and for inputting input data to a data input/output line pair adjacent to the corresponding data input/output line pair.
In another preferred embodiment, the present invention includes a plurality of memory cell array banks, a plurality of memory cell array blocks of each the memory cell array banks, a plurality of partial blocks of each of the memory cell array blocks connected to each of a plurality of data input/output line pairs, a predetermined number of redundant partial blocks of each of the memory cell array blocks connected to each of a predetermined number of redundant data input/output line pairs, a plurality of partial blocks according to a column address group of each of the partial blocks and a predetermined number of redundant partial blocks according to a column address group of each of a predetermined number of redundant partial blocks, a control signal generation means for generating selection control signals by column address groups for selecting a plurality of partial blocks according to the column address group in response to an automatic refresh command, an address setting means for setting redundant control signal by column address groups and defective address in response to the selection control signal by column address groups, a plurality of decoders and shifting control signal generation means for generating a plurality of shifting control signals for controlling shifting of the data input/output line pairs and the redundant data input/output line pairs by decoding the redundant control signal and the defective address, and a plurality of switching means for outputting data output from a data input/output line pair adjacent to a corresponding data input/output line pair in response to each of the shifting control signals and for inputting input data to a data input/output line pair adjacent to th

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