Semiconductor memory device and redundancy method therefor

Details Semiconductor memory device and redundancy method therefor Semiconductor memory device and redundancy method therefor

2011-07-26

2011-07-26

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S148000, C365S158000, C365S163000, C365S175000

Reexamination Certificate

active

07986575

ABSTRACT:
A memory cell array is formed by arranging memory cells at intersections of plural first wirings and plural second wirings, and a rectifying element and a variable resistive element are connected in series in the memory cell. The variable resistive element has at least a first resistance value and a second resistance value that is higher than the first resistance value. The control circuit selectively drives the first wirings and the second wirings. The control circuit can perform a short-circuit failure countermeasure program operation. In the short-circuit failure countermeasure program operation, the variable resistive element of the memory cell whose rectifying element is in a short-circuit failure state is programmed from the first resistance value to the second resistance value.

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patent: 2002-541613 (2002-12-01), None
patent: WO 00/62301 (2000-10-01), None

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