Semiconductor memory device and redundancy judging method

Details Semiconductor memory device and redundancy judging method Semiconductor memory device and redundancy judging method

2002-10-07

2004-11-16

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189070

Reexamination Certificate

active

06819605

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the reduction of current consumption in redundancy judging unit of a semiconductor memory device, and more particularly to the reduction of current consumption when a static-type redundancy judging unit is used.
2. Description of the Related Art
Conventionally, with respect to a semiconductor memory device, the demand for finer circuit design and large capacity have been accelerated. However, the occurrence probability of defects on layout derived from particles or the like has been increased along with the finer circuit design, while the occurrence probability of defects has been also increased derived from the increase of die size along with the increase of capacity whereby, as a whole, there has been observed a tendency that the number of defects in memory cells has been increasing. Accordingly, there has been observed a tendency that the number of defective memory cells to be relieved is increasing due to the failure of characteristics derived from defects. Along with the increase of the number of defective memory cells, the number of redundancy judging circuits for replacing the defective memory cells with auxiliary memory cells is increased whereby the current consumption caused by the redundancy judging operation has been increasing. Since the judging operation is performed each time an access operation to the memory cells is performed, the reduction of current consumption caused by the redundancy judging operation has been demanded.
Further, in the technical field of portable equipment which has been sharply developed recently, along with the increase of functions incorporated into the portable equipment, a semiconductor memory device having a large capacity has been demanded and hence, a dynamic random access memory (hereinafter referred to as “DRAM”) has been adopted in view of the high integration density of a memory cell structure. The DRAM which is mounted in the portable equipment has been subjected to the refreshing operation such as the self-refreshing operation or the like even in the non-access period during standby time. Here, with respect to the current consumption at the time of refreshing operation, except for the selection of memory cell and the operation of a memory cell core section such as the amplification of cell data, the judging operation performed by the redundancy judging circuit occupies a large portion of the operation of peripheral circuits. Accordingly, with respect to the portable equipment such as a portable telephone or a digital camera which is held in the standby state for a long period, to enhance the continuous service time characteristics at the time of driving a battery, it is dispensable to reduce the current consumption at the standby state. Accordingly, the reduction of the current consumption of the redundancy judging operation at the time of refreshing operation in the semiconductor memory device such as DRAM or the like is extremely important.
To cope with the demand for the reduction of current consumption of the above-mentioned redundancy judging operation, in the first prior art shown in
FIG. 9
corresponding to Japanese Laid-open Patent Publication No. 5-252998, a power-on signal PON is set in low level when the power is turned on. When a fuse
603
is cut, an output of a latch circuit
604
is set in high level, p-channel transistors
608
,
609
and
610
are turned on so that the redundancy judging function realized by a redundancy address judging circuit
300
becomes effective. When the fuse
603
is not cut, the output of the latch circuit
604
is set in low level and the three p-channel transistors
608
,
609
and
610
are turned off so that the redundancy address judging circuit
300
becomes inoperative. When there exists no defective memory cell or an auxiliary memory cell is not used, the current consumption is reduced by stopping the operation of the redundancy address judging circuit
300
.
Further, as the second prior art, comparing/selecting unit disclosed in Japanese Laid-open Patent Publication No. 3-307898 is shown in FIG.
10
. Storing of defective cell addresses to fuse elements F
110
to Fn
20
of a comparing/selection circuit
100
is performed by cutting the fuse elements which correspond to a bit “1” among bits A
1
to An or complements thereof A
1
b
to Anb of corresponding input address codes. At a point of time that an input address code which coincides with the address of the defective cell is supplied to a comparing/selecting circuit
100
, the bit “1” is received by a gate electrode and the fuse elements which are connected to transistors Q
110
to Qn
20
to be turned on are all cut so that a driving voltage from a driving pulse supply circuit
120
holds the value as it is at an output node N
100
. When the input address code does not coincide with the address of the defective cell, since there exists at least one transistor which is connected to the fuse element which is not cut and receives the bit “1” at the gate electrode, the potential of the output node N
100
is lowered to a ground potential. The supply of the driving voltage to the output node N
100
is performed through the fuse element F
100
and the transistor Q
100
of a driving pulse supply circuit
120
. However, with respect to the surplus comparing/selecting circuit
100
, the fuse element F
100
is cut so as to stop the generation of an electric current which flows into the output node N
100
whereby the consumption of power can be saved.
Further, in the portable equipment, it is necessary to reduce the current consumption during standby time as much as possible. Accordingly, with respect to a DRAM served for operation, there have been proposed several methods for reducing the current consumption generated by the refreshing operation which is a major factor causing current consumption during standby time as much as possible. Relieving of defective memory cells using a so-called refreshing redundancy is one of such measures.
In FIG.
11
and
FIG. 12
, a concept of refreshing redundancy is shown. In
FIG. 11
, a memory cell core section
1000
of a semiconductor memory device is shown schematically. The memory cell core section
1000
is constituted of a memory cell array section
1100
and an auxiliary memory cell array section
1200
. In the memory cell array section
1100
, memory cells (MC
0
to MC
2
and the like) are properly arranged at intersections of word lines WL
0
to WLn and bit lines BL
0
to BLn. In the auxiliary memory cell array section
1200
, redundancy memory cells (SMC
0
and the like) are properly arranged at intersections of redundancy word lines SWL
0
to SWLm and redundancy bit lines SBL
0
to SBLn.
Further,
FIG. 12
schematically shows the characteristic distribution of memory cells using a data holding time tREF of the memory cells (MC
0
to MC
2
and the like) as a parameter. Using a data holding time t
1
(tREF=t
1
) as a lower limit value of data holding characteristics, the memory cells (MC
0
and the like) which have the data holding time tREF longer than the lower limit value constitute normal memory cells. The memory cells (MC
2
and the like) having characteristics in which the data holding time tREF is below the lower limit value t
1
and reaches a lowermost limit value t
0
(lower limit value in a usual DRAM) constitute memory cells having defective tREF characteristics. The memory cells (MC
1
and the like) whose data holding time tREF is equal to or below the lowermost limit value t0 include, as shown in
FIG. 11
, the memory cells which are not accessible due to a layout defect such as the disconnection of the word line WL
1
and these memory cells constitute access disabled memory cells (MC
1
and the like).
In the memory cells, since a charge stored in a memory cell capacitor is lowered below the reference voltage in the data holding time tREF and the data is dissipated, it is necessary to set a period of refreshing within the data holding time tREF. Accordingly, the memory cells (MC
1
,

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