Semiconductor memory device and read and write methods thereof

Details Semiconductor memory device and read and write methods thereof Semiconductor memory device and read and write methods thereof

2000-11-29

2002-06-18

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060, C365S230010, C365S230080

Reissue Patent

active

RE037753

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present-invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device having improved bandwidth input and output using an external synchronous signal and read/write methods thereof.
The present application for a semiconductor memory device for exchanging data by using a synchronous signal and read/write methods thereof, is based on Korean Application No. 29574/1995 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
Recently, while the operating frequency of microprocessors continues to increase in computer systems, the operating frequency of a semiconductor memory device has increased relatively slowly. This results in a memory bottleneck that hampers performance of the computer. One solution for relieving the memory bottleneck is to increase the width of the memory bus so that the amount of the data or word size between the computer and semiconductor memory device is increased. However, at the same time, increasing the capacity of the unit memory results in reducing the granularity as a minimum memory unit.
For example, in the case of a memory system in which the actual wiring width of the memory bus is 64 bits, with using a 4 mega bit memory of which the data wiring width is 8, the memory is incremented by a 32 mega bit unit. But, when using a 256 mega bit memory where the bus width is 8, increasing the bus width to 64 provides a memory increment of 2048 mega bit. For this reason, apart from enlarging the capacity of the unit memory, it is also known to increase the data wiring width of the unit memory in order to resolve the problem of the granularity without sacrificing performance of the system. Thus, as can be seen in the above example, the granularity as the minimum memory unit without deterioration on the performance thereof can be formed by increasing the data wiring width of the unit memory to 64. However, such a method gives rise to the following problems: First, an increment of the chip size follows from the increase in the number of pads in a circuit. Second, an increment in power consumption follows as well due to the increase of the circuit size, the increased number of the conductors, and the increase in the number of output terminals, each of which should includes a driver having a large load, and so on. Accordingly, it is not desirable to use the above method to improve the I/O bottleneck in a semiconductor memory.
An alternative approach is to increase the operating frequency of the memory. In other words, as noted beforehand, by increasing the operating frequency of the 256 mega bit memory in which the data wiring width is 8, the granularity remains equal to one unit (word) of the memory with no deterioration in performance. Moreover, when using a fast memory as described above, the performance of the memory system can easily be augmented by arranging a plurality of smaller word size (unit) memories in parallel. A synchronous memory is exemplary of increasing the operating frequency of the unit memory. In a memory system constructed with synchronous memory, control signals and data signals for operating the memory, such as an address signal, a chip select signal, a write enable signal etc., are synchronized with a global clock for controlling the overall memory system including a memory and a memory controller.
Using the synchronous memory, all of the control signals operate in synchronism with the global clock. Consequently, although data having N times the size of the memory port word size can accessed in the memory during one clock period, it is impossible to exchange the data at a speed greater than the frequency of the global clock. By data “exchange” we mean a read or a write operation through a memory port or terminal. In addition, increasing the frequency of the global clock to improve the bandwidth of the data exchange also increases the operating frequency of the overall memory circuit, thereby incrementing the operating power of the memory. Further, there is a problem in that the maximum operating frequency of the global clock is limited by the phase difference of the clock generated between each clock wiring of the memory and controller at a specific time.
FIG. 1
is a block diagram illustrating the construction of a prior art semiconductor memory device. With reference to
FIG. 1
, a system clock signal CLK and a clock enable signal CKE are transmitted to a control clock generator
21
, the above signals CLK and CKE being supplied from outside the semiconductor memory device. Also, a chip select signal CS/, a write enable signal WE/, a row address strobe signal RAS/, and a column address strobe signal CAS/ are input to the control clock generator
21
(the virgule “/” being used herein to designate an active low signal, as indicated by a horizontal bar over the corresponding signal name in the drawing). A write data signal DATA is delivered from the exterior to a data-in buffer
22
in synchronism with the system clock CLK. A read data signal DATA is delivered from a data-out buffer
23
to the exterior. The DATA terminal or port of course may be multiple bits wide.
The control clock generator
21
generates internal control signals, some of which are synchronized to the system clock CLK, in response to the various external control signals as long as the clock enable signal CKE is asserted. A control signal
6
generated from the row address strobe signal RAS/ is transmitted to a set input terminal of a row (address) buffer
11
, thereby latching a row address from an address signal ADDR. ADDR is a multiple-bit address input to an address terminal or port. Similarly, a control signal
7
generated from the column address strobe signal CAS/ is transmitted to a set input terminal of a column buffer
13
, for latching the address signal ADDR therein. An output signal of the row buffer
11
is transmitted to an input terminal of a row decoder
12
. The row decoder selects or drives a corresponding word line of a memory cell array
15
, all of which is conventional. An output signal of the column buffer
13
is transmitted to an input terminal of the column decoder
14
and thus, drives a column selection line of the memory cell array
15
.
In a write operation, externally applied DATA is latched in the data-in buffer
22
(also referred to as a data input buffer, or simply “input buffer”), as further explained later, and the contents of the data-in buffer
22
is written into the memory cell array
15
through sense amplifiers
16
. Conversely, in a read operation, data from the memory cell is amplified by the sense amplifier
16
and latched in the data-out buffer (or “output buffer”)
23
. The data received from the exterior (i.e. write data) or the data transferred to the exterior (read data) is synchronized with the system clock CLK, by control signals
5
provided by the control clock generator circuit
21
. Operation of the memory device of
FIG. 1
is further illustrated in the timing diagrams of
FIGS. 2A and 2B
. Specifically,
FIG. 2A
shows a read cycle and a write cycle and
FIG. 2B
shows the read and write operations in a page mode cycle.
The memory as described above can increase the margin of the setup and the hold time for latching the signal, by operating all of inputs/outputs such as the control signals, the address signal, and the data in synchronism with the system clock CLK, and increasing the system clock operating frequency. However, in case of using the memory of
FIG. 1
, now that all of signals operate in synchronism with the system clock CLK, even if data having N times the memory internal word size can be accessed during a period of one system clock, it is impossible to exchange the data at a speed greater than the frequency of the system clock CLK. In other words, the I/O bandwidth is limited by the system clock frequency in the synchronized system. In addition, increasing the frequency of the system clock CLK to improve the I/O bandwidth increases the operating frequency of th

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