Semiconductor memory device and operation method thereof

Details Semiconductor memory device and operation method thereof Semiconductor memory device and operation method thereof

2008-06-30

2010-11-30

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S193000, C365S189080, C365S233110

Reexamination Certificate

active

07843744

ABSTRACT:
A semiconductor memory device that generates a data strobe reset signal for preventing ring-back of a data strobe signal, and an operation method thereof. The semiconductor memory device includes a pulse signal generating unit for generating first and second pulse signals by synchronizing a write instruction with first and second internal clock signals, a reset signal generating unit for generating a reset signal having an activation width setup in response to the first and second pulse signals, and a data strobe reset signal generating unit for generating a data strobe reset signal by shifting the second pulse signal as much as a predetermined burst length and limiting an activation period of the data strobe reset signal in response to the reset signal.

REFERENCES:
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patent: 6525988 (2003-02-01), Ryu et al.
patent: 2008/0205186 (2008-08-01), Kim et al.
patent: 2010/0103746 (2010-04-01), Ma
patent: 1020010046340 (2001-06-01), None
patent: 1020070119378 (2007-12-01), None
Notice of Allowance issued from Korean Intellectual Property Office on May 26, 2009 with an English Translation.

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