Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2003-07-09
2004-08-24
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S104000, C365S103000, C365S230060
Reexamination Certificate
active
06781902
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a testing method and relates to, for example, a technique effective for use in a technique of testing a one-chip microcomputer having therein a memory circuit.
By investigation of known arts made after the present invention has been achieved, the following disclosed techniques are reported as techniques related to the present invention. Japanese Unexamined Patent Publication Nos. Hei 8(1996)-339696 and Hei 8(1996)-339699 disclose a dynamic RAM in which all of word lines are selected or word lines are alternately selected to apply a stress on a word line. Japanese Unexamined Patent Publication No. Hei 11(1999)-238397 discloses a memory in which odd-numbered (or even-numbered) or all of word lines can be selected at the time of burn-in. Japanese Unexamined Patent Publication No. Hei 7 (1995)-262798 discloses a memory in which a stress can be applied to all of word lines or every other word line. Japanese Unexamined Patent Publication No. Hei 8 (1996)-273394 discloses a memory in which a stress is applied between neighboring word lines and, after that, a stress is applied to all of word lines.
SUMMARY OF THE INVENTION
In a one-chip microcomputer having a mask ROM (Read Only Memory) or the like in which important data such as a program is stored, when the mask ROM has a defect, an error occurs in a data process or the like and the whole becomes defective. Particularly, in a one-chip microcomputer requested to have high reliability such as one for a vehicle, it is important to assure reliability of the mask ROM to assure high reliability. In the mask ROM of the one-chip microcomputer, if a defect such as a short circuit exists in word lines and bit lines, basically, the defect can be detected as a read error. For example, as shown in
FIG. 12
, when short circuits shown as resistance exist in bit lines B
1
and B
2
and word lines W
1
and W
2
, the defects of the short circuits can be detected as read errors at the time of selecting the bit line B
1
or word line W
1
at the time of changing a read address.
However, when the defect of the short circuit is uncertain, that is, when a short circuit having a relatively large resistance value exists in the word lines and bit lines, there are a case where a read error is detected and a case where a read error is not detected when the bit line B
1
or word line W
1
as shown in
FIG. 12
is selected. Consequently, to detect such an uncertain defect of a short circuit as described above, there are problems such that the number of combinations of testing conditions (measured voltage, temperature, and the like) for detection in testing increases. Moreover, a defect which occurs once in a plurality of times of reading operations under the same test conditions cannot be detected with reliability even testing is made for long time.
An object of the invention is to provide a semiconductor device and a testing method capable of easily detecting a short circuit in a memory circuit with high precision. Another object of the invention is to provide a semiconductor device and a testing method capable of efficiently detecting a short circuit in a memory circuit. The above and other objects and novel features of the invention will become apparent from the description of the specification and appended drawings.
A representative one of inventions disclosed in the specification will be described briefly as follows. A memory circuit in which memory cells are disposed at intersections of a plurality of word lines and a plurality of bit lines performs, in a test mode, an operation of applying a predetermined potential to neighboring ones of a plurality of word lines or bit lines, an operation of selecting a plurality of word lines and applying a ground potential of the circuit to all of the plurality of bit lines, and an operation of setting all of a plurality of bit lines at a predetermined potential corresponding to the selection level of the word lines and making all of the plurality of word lines into a non-selection state. By measuring current flowing in a power supply terminal of the semiconductor device, a short circuit between word lines, a short circuit between bit lines, a short circuit between a word line and a bit line, and the like are detected.
REFERENCES:
patent: 5615164 (1997-03-01), Kirihata et al.
patent: 5619460 (1997-04-01), Kirihata et al.
patent: 5657282 (1997-08-01), Lee
patent: 5808949 (1998-09-01), Arimoto
patent: 5905690 (1999-05-01), Sakurai et al.
patent: 5963491 (1999-10-01), Arimoto
patent: 6055200 (2000-04-01), Choi et al.
patent: 6084808 (2000-07-01), Lim et al.
patent: 6651196 (2003-11-01), Iwase et al.
patent: 07-262798 (1995-10-01), None
patent: 08-273394 (1996-10-01), None
patent: 08-339696 (1996-12-01), None
patent: 08-339699 (1996-12-01), None
patent: 11-238397 (1999-08-01), None
Handa Naoki
Kobayashi Kenji
Oumiya Atsuo
Tanaka Kouta
Miles & Stockbridge P.C.
Renesas Technology Corp.
Tran Andrew Q.
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