Semiconductor memory device and method of testing same

Details Semiconductor memory device and method of testing same Semiconductor memory device and method of testing same

2006-10-03

2006-10-03

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S200000, C365S201000

Reexamination Certificate

active

07117406

ABSTRACT:
A semiconductor memory device is provided which includes: a plurality of memory cells each formed by latch means; gated clock circuits for writing identical data to all of the memory cells in response to a simultaneous writing signal supplied thereto; inverters for inverting data outputted from the memory cells; and selectors for selectively writing the inverted data to the memory cells.

REFERENCES:
patent: 5457696 (1995-10-01), Mori
patent: 5537631 (1996-07-01), Wong et al.
patent: 5883843 (1999-03-01), Hii et al.
patent: 6536003 (2003-03-01), Gaziello et al.
patent: 6694461 (2004-02-01), Treuer

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