Semiconductor memory device and method of testing same

Details Semiconductor memory device and method of testing same Semiconductor memory device and method of testing same

2011-03-15

2011-03-15

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S230050

Reexamination Certificate

active

07907459

ABSTRACT:
Disclosed is a semiconductor memory device in which a cell is connected to word lines of at least first and second ports, and control of timing of activation of the word lines of the first and second ports is performed based upon first and second clock signals, respectively, comprising first and second test control signals in correspondence with the first and second clock signals that control the respective timings of activation of the word lines of the first and second ports. With regard to the cell with the first and second ports being selected, when the first test control signal is in an activated state and the second test control signal is in a deactivated state, control is exercised so as to mask the second clock signal and, responsive to the first clock signal, activate the first and second word lines simultaneously. When the second test control signal is in an activated state and the first test control signal is in a deactivated state, control is exercised so as to mask the first clock signal and, responsive to the second clock signal, activate the first and second word lines.

REFERENCES:
patent: 5530677 (1996-06-01), Grover et al.
patent: 6151266 (2000-11-01), Henkels et al.
patent: 6876595 (2005-04-01), Bhavnagarwala et al.
patent: 7042792 (2006-05-01), Lee et al.
patent: 1-296486 (1989-11-01), None

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