Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2007-02-27
2007-02-27
Mai, Son L. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S230030
Reexamination Certificate
active
11051346
ABSTRACT:
A semiconductor memory device comprises at least one memory plane in which a plurality of memory blocks are arranged, and a block decoder circuit which decodes a block address signal for selecting the memory block from the memory plane and outputs block selection signals for selecting the memory block, as well as puts all of the block selection signals in a selected state and output them in a predetermined test mode, and a block selection signal inversion circuit which inverts or non-inverts signal levels of the block selection signals.
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European Search Report mailed Jul. 4, 2005 for European Patent Application No. 05250629.2, 4 pages.
Mori Yasumichi
Watanabe Masahiko
Mai Son L.
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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