Semiconductor memory device and method of selecting word...

Details Semiconductor memory device and method of selecting word... Semiconductor memory device and method of selecting word...

2002-06-13

2004-06-08

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230040, C365S230060, C365S230080, C365S185050, C365S185230

Reexamination Certificate

active

06747908

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of selecting a word line thereof.
2. Description of Related Art
A conventional semiconductor memory device having a sub word line includes a plurality of memory blocks. In such a semiconductor memory device, when a row address is input in response to a row address strobe signal, one global word line is selected. When one global word line is selected, among a plurality of sub word lines, one sub word line corresponding to the selected global word line is selected. And, when a column address is input in response to a column address strobe signal, a bit line pair is selected. At this time, a selected memory cell in one memory cell array block receives or outputs a data. In other words, in the conventional semiconductor memory device having a sub word line, when one sub word line in one memory cell array block is selected, sub word lines of all partial blocks that constitute the memory cell array block are selected. As a result, since sub word lines of the memory cell array block that have not to be selected are selected, power consumption is high.
Also, the conventional semiconductor memory device having a sub word line receives a row address before receiving a column address to perform a read operation and a write operation, and thus cannot select a sub word line of a certain memory cell array partial block in a memory cell array block.
Meanwhile, a fast cycle random access memory (FCRAM) device simultaneously receives a row address and a column address to select partial blocks that constitute the memory cell array block to select a sub word line in the partial blocks. However, the FCRAM device can greatly improve a data transmission rate but has a problem in that a chip size becomes large.
A high-speed RAM device disclosed in the U.S. Pat. No. 6,108,243 selects only sub word lines in selected partial blocks among partial blocks that constitute a memory cell array block. However, the RAM device can reduce power consumption but has a problem in that a layout area size is increased.
SUMMARY OF THE INVENTION
An embodiment of the present invention comprises a semiconductor memory device. The device includes a plurality of memory cell array blocks each including a plurality of partial blocks in one of either a first or a second partial block group, a plurality of global word lines and a plurality of sub word lines in one of either a first or second sub word line group, corresponding to each of the plurality of the global word lines. In partial blocks of the first partial block group, sub word lines of the first sub word line group are connected to sub word lines of the first sub word line group of a previous block, and sub word lines of the second sub word line group are connected to sub word lines of the second sub word line group of a next partial block. ln partial blocks in the second partial block group, sub word lines of the first sub word line group are connected to sub word lines of the first sub word line group of the next partial block, and sub word lines of the second sub word line group are connect to sub word lines of the second sub word line group of a previous partial block. A control means is provided for selecting sub word lines of a corresponding partial block and sub word lines of a neighboring partial block connected to the sub word lines of the corresponding partial block when the corresponding partial block is selected in response to externally applied row and column address.
An alternative embodiment of the present invention provides a semiconductor memory device, comprising: a plurality of memory cell array blocks each including a plurality of partial blocks, a plurality of global word lines, and odd-numbered and even-numbered sub word lines corresponding to each of the plurality of the global word lines, the odd-numbered sub word lines of each of odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the previous neighboring partial blocks, the even-numbered sub word lines of each of the odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the even-numbered sub word lines of each of the next neighboring partial blocks, the odd-numbered sub word lines of each of even-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the next neighboring partial blocks, the even-numbered sub word lines of each of the even-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the even-numbered sub word lines of each of the previous neighboring partial blocks; and a control means for selecting sub word lines of a corresponding partial block and sub word lines of a neighboring partial block connected to the sub word lines of the corresponding partial block when the corresponding partial block is selected in response to externally applied row and column address.


REFERENCES:
patent: 6108243 (2000-08-01), Suzuki et al.
patent: 6215692 (2001-04-01), Kang
patent: 6400639 (2002-06-01), Ji et al.

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