Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-23
2002-12-31
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000
Reexamination Certificate
active
06501119
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for producing the same, more particularly relates to a dynamic random access memory (DRAM) or other semiconductor memory device having a storage node electrode and a method for producing the same.
2. Description of the Related Art
In recent very large scale integrated circuits (VLSI) and other semiconductor devices, reductions of scale of 70% have been realized in three years. Higher degrees of integration and higher performance have been achieved. For example, DRAMs have a memory cell structure having a switching use metal-oxide-semiconductor field effect transistor (MOSFET) and a memory capacitor. They have become increasingly miniaturized and reduced in size in recent years and have become increasingly large in capacity and higher in degree of integration as process drivers in semiconductor devices, for example, with DRAMs having a storage capacity of 1 Gb being announced at the academic level. Along with the miniaturization, the area of the memory cells has been reduced and the area occupied by the memory capacitors has been reduced.
However, in order to secure a sufficient operating margin and secure a tolerance to soft error due to alpha rays so as to raise the reliability of the stored data, the storage capacity Cs of the memory capacitor is held at a constant value of 20 to 30 fF per bit regardless of the generation of the DRAM.
Accordingly, irrespective of the fact that the area occupied by the memory capacitor has been reduced along with the miniaturization, the required amount of storage capacity Cs must be secured. Various attempts have been made to deal with this.
For example, other than the method of reducing the thickness of a capacitor insulating film so as to increase the storage capacity, a method has been developed of using as the capacitor insulating film tantalum oxide (Ta
2
O
5
), BST, STO, or the like having a high dielectric ratio in place of an ON film (or ONO film) comprising a composite film of a silicon nitride film and a silicon oxide film so as to improve the materials comprising the capacitor insulating film and increase the storage capacity of the capacitor.
On the other hand, improvements have been made to the electrode structure of the capacitor as well. Capacitors having various structures have been developed. A memory capacitor comprises a storage node electrode (electrode connected to the transistor of the capacitor), a plate electrode (grounded electrode of the capacitor), and a capacitor insulating film between them. By increasing the surface area of the storage node electrode and the plate electrode, it is possible to increase the storage capacity of the capacitor.
A planer type having a planar structure has been used in the related art, but at present, generally the storage node electrode is made three-dimensional to obtain a more complex shape, the side wall surfaces of the storage node electrode etc. are utilized, and therefore the surface area of the storage node electrode is increased to increase the storage capacity without increasing the occupied area of the capacitor. As a three-dimensional storage node electrode, there are for example a stack type, a trench type, etc.
In the trench type, the storage node electrode is formed in the depth direction with respect to the substrate, so it is necessary to investigate the adverse influence due to digging into the substrate. On the other hand, the stack type can be classified into two types, that is, the capacitor-over-bit line (COB) and the capacitor-under-bit line (CUB) type. Among them, in the case of the COB stack type, since the capacitor (storage node electrode) is formed after the bit line, there is the advantage that the largest capacitor (storage node electrode) determined by the miniaturization can be formed in the cell region.
As the COB stack type described above, a variety of types have been developed such as the pedestal stack type, fin type, and cylinder type (crown type). As the cylinder type, other than a type having a single cylindrical part, a type having a double cylindrical part has been developed. Further, similarly, a method of coarsening the storage node electrode surface in order to increase the surface area and a method of controlling the polycrystalline silicon electrode-forming temperature to providing semispherical roughness on the surface have been developed.
Among them, the cylinder type storage node electrode can make effective use of the peripheral length of the electrode as the surface area, therefore, despite the reduction of the occupied area, the storage capacity is easily secured. This makes it one of the electrode structures best suited to the miniaturization, increase of degree of integration, and reduction of size of semiconductor memory devices. The methods for forming cylinder type storage node electrodes may be roughly classified into methods of forming a side wall-shaped electrode in the side wall portion of for example a recessed type oxide film and methods of forming the electrode material at the inner wall of a recessed type oxide film. In general, the latter enables a larger exposure margin in lithography and a larger margin with respect to the focus depth, so is advantageous with respect to further miniaturization.
The methods of forming cylinder type storage node electrodes of the related art, however, suffer from several problems such as a difficulty in exposing the top face of the storage node contact plug and connection failure between the storage node contact plug and the storage node electrode and, even when there is no connection failure, inadvertent etching of the inter-layer insulating film and, in the worst case, a short circuiting of the bit line and the storage node. These will be explained in further detail later, along with the method of production of the related art, with reference to the attached drawings.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a DRAM or other semiconductor memory device having a memory capacitor wherein provision is made of a high quality storage node electrode and storage node contact plug enabling prevention of the connection failure between the storage node contact plug and the storage node electrode and prevention of the removal of the insulating film below the etching stopper which is a cause of short-circuiting and a method for producing the same.
To attain the above object, according to a first aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of memory cells each having a memory capacitor having a storage node electrode and a transistor, comprising a substrate, a transistor formed on said substrate, a first insulating film formed on said substrate covering said transistor, a storage node contact hole formed in said first insulating film and reaching a source and drain region of said transistor, a storage node contact plug buried in said storage node contact hole, a storage node electrode formed connected to said storage node contact plug, a second insulating film formed above said first insulating film in the gap portion of said storage node electrodes, a capacitor insulating film formed above said storage node electrode, and a plate electrode formed above said capacitor insulating film, said storage node electrode and said storage node contact plug being formed connected at least at part of the top surface and side surface of said storage node contact plug.
That is, according to the semiconductor memory device of this aspect of the present invention, the storage node electrode and the storage node contact plug are formed connected at least at part of the top surface and the side surface of the storage node contact plug. In the related art, they were connected at only the top surface of the storage node contact plug, therefore when the plug loss was large, it was sometimes difficult to sufficiently expose the top surface of the storage node contact plug. By connecting them at part
Kananen Ronald P.
Nguyen DiLinh
Radar Fishman & Grauer
LandOfFree
Semiconductor memory device and method of producing same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device and method of producing same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and method of producing same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2955739