Semiconductor memory device and method of generating chip...

Details Semiconductor memory device and method of generating chip... Semiconductor memory device and method of generating chip...

2007-07-10

2009-12-15

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C365S189030, C711S103000

Reexamination Certificate

active

07633785

ABSTRACT:
Provided are a semiconductor memory device and a method of generating a chip enable signal thereof. The device includes a plurality of memory chips and an interface chip that are stacked. Each of the memory chips includes a control signal setting unit, which sets input signals applied to first and second input nodes as less significant 2-bit control signals of n-bit control signals, performs a logic AND operation on the less significant 2-bit control signals to generate AND operated signals, performs a logic XOR operation on each of the AND operated signals and each bit signal of more significant n−2-bit input signals applied to third to n-th input nodes to set the n−2-bit control signals, outputs the signal applied to the second input node through a first output node, inverts the signal applied to the first input node to output the inverted signal through a second output node, and outputs the more significant n−2-bit input signals through third through n-th output nodes, respectively. The first through n-th output nodes of one of two adjacent memory chips are respectively connected to the first through n-th input nodes of the other of the two adjacent memory chips.

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