Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate
1999-07-26
2001-05-15
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Fet configuration adapted for use as static memory cell
C257S288000, C257S368000
Reexamination Certificate
active
06232670
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular, an SRAM and a method of fabricating the same.
2. Description of Background Art
A six transistor-type SRAM comprises memory cells including two load transistors, two driver transistors, and two transfer transistors. Active regions of each memory cell are isolated from active regions of the adjoining cells by an element isolation region comprising a field oxide layer and the like.
A phenomenon in which current flows between the element isolation regions is referred to as punch-through. Punch-through causes malfunction of the SRAM. According to the demand for a reduced cell size, the width of the element isolation region has become narrower. Punch-through occurs more easily as the width of the element isolation region becomes narrower.
SUMMARY OF THE INVENTION
The present invention has been achieved to overcome the above problems. An object of the present invention is to provide a semiconductor memory device which can prevent punch-through between memory cells, and a method of fabricating the same.
The semiconductor memory device according to the first aspect of the present invention including: a semiconductor substrate having a main surface; and first and second load transistors and first and second driver transistors formed on the main surface, comprises first and second memory cells and a second element isolation region.
Each of the first and second memory cells comprises:
a first load transistor active region formed on the main surface and to be an active region for the first load transistor;
a second load transistor active region formed on the main surface and to be an active region for the second load transistor;
a first driver transistor active region formed on the main surface and to be an active region for the first driver transistor;
a second driver transistor active region formed on the main surface and to be an active region for the second driver transistor;
a first element isolation region formed on the main surface and isolating the first load transistor active region from the first driver transistor active region;
a first conductive layer extending from an area on the first load transistor active region to an area on the first driver transistor active region, and to be a gate electrode for the first load transistor and the first driver transistor;
a second conductive layer which diverges from the first conductive layer on the first element isolation region and is electrically connected to the second driver transistor active region; and
a third conductive layer being electrically connected to the first load transistor active region and extending to an area on the second driver transistor active region across an area on the second load transistor active region, and to be a gate electrode for the second load transistor and the second driver transistor.
The second element isolation region is formed on the main surface and isolates the first and second load transistor active regions of the first memory cell from the first and second load transistor active regions of the second memory cell.
A pattern of the first, second, and third conductive layers of the second memory cell is a rotated pattern of the first, second, and third conductive layers of the first memory cell at an angle of 180 degrees around an axis perpendicular to the main surface.
Such a rotated pattern at 180 degrees can prevent punch-through between the first and second load transistor active regions of the second memory cell and the first and second load transistor active regions of the first memory cell.
Specifically, the distance between a drain region in the first and second load transistor active regions of the first memory cell and a drain region in the first and second load transistor active regions of the second memory cell can have almost the same value as the sum of the widths of the second element isolation region and the third conductive layer. The existence of the third conductive layer can make this distance larger, so that punch-through can be prevented in this region.
According to the second aspect of the present invention, a semiconductor memory device, comprising a memory cell array having a plurality of memory cells including first and second load transistors and first and second driver transistors, has the following configuration.
Each of the memory cells comprises:
a semiconductor substrate having a main surface;
a first load transistor active region formed on the main surface and to be an active region for the first load transistor;
a second load transistor active region formed on the main surface and to be an active region for the second load transistor;
a first driver transistor active region formed on the main surface and to be an active region for the first driver transistor;
a second driver transistor active region formed on the main surface and to be an active region for the second driver transistor;
a first element isolation region formed on the main surface and isolating the first load transistor active region from the first driver transistor active region;
a first conductive layer extending from an area on the first load transistor active region to an area on the first driver transistor active region, and to be a gate electrode for the first load transistor and the first driver transistor;
a second conductive layer which diverges from the first conductive layer on the first element isolation region and is electrically connected to the second driver transistor active region; and
a third conductive layer being electrically connected to the first load transistor active region and extending to an area on the second driver transistor active region across an area on the second load transistor active region, and to be a gate electrode for the second load transistor and the second driver transistor.
The memory cell array comprises:
first and second lines including the memory cells; and
a second element isolation region which isolates the first line from the second line.
A pattern of the first, second, and third conductive layers of each of the memory cells in the second line is a rotated pattern of the first, second, and third conductive layers of each of the memory cells in the first line at an angle of 180 degrees around an axis perpendicular to the main surface.
The configuration of the semiconductor memory device according to the second aspect of the present invention is from the viewpoint of a memory cell array. Punch-through can be prevented for the same reason as described in the previous aspect.
The semiconductor memory device according to the second aspect of the present invention preferably has the following configuration. The second load transistor active region of each of the memory cells in the first line comprises a first facing region which faces the first load transistor active region of each of the memory cells in the second line with the second element isolation region interposing therebetween, and a pattern of the third conductive layer of each of the memory cells in the first line is formed across an area on the first facing region. The second load transistor active region of each of the memory cells in the second line comprises a second facing region which faces the first load transistor active region of each of the memory cells in the first line with the second element isolation region interposing therebetween, and a pattern of the third conductive layer of each of the memory cells in the second line is formed across an area on the second facing region.
The pattern of the third conductive layer of each of the memory cells in the first line is formed across an area on the first facing region. Therefore, the existence of the third conductive layer can make the distance between a drain region in the first load transistor active region of each of the memory cells in the second line, and a drain region in the second load transistor active region of each of the memory cells in the first line larger. Specifically, this distance can have
Karasawa Junichi
Kumagai Takashi
Tanaka Kazuo
Watanabe Kunio
Hogan & Hartson LLP
Lee Eddie C.
Richards N. Drew
Seiko Epson Corporation
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