Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...
Reexamination Certificate
2011-08-30
2011-08-30
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including high voltage or high power devices isolated from...
C257S506000, C257SE21230
Reexamination Certificate
active
08008742
ABSTRACT:
Provided are a semiconductor memory device whereby generation of dishing during planarization of a peripheral circuit region is suppressed, and a method of fabricating the semiconductor memory device. The semiconductor memory device includes a semiconductor substrate comprising a first active area in a memory cell region and a second active area in a peripheral circuit region; a plurality of first isolation films and a plurality of second isolation films protruding from a surface of the semiconductor substrate and defining the first active area and the second active area, respectively; and at least one polish stopper film formed within the second active area and protruding from the surface of the semiconductor substrate.
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patent: 6281050 (2001-08-01), Sakagami
patent: 2004/0195632 (2004-10-01), Sato
patent: 2009/0039402 (2009-02-01), Jung et al.
patent: 2001-176959 (2001-06-01), None
patent: 2002-198419 (2002-07-01), None
patent: 10-2007-0044284 (2007-04-01), None
Baek Su-in
Choi Seung-wook
Kim Hong-Soo
Budd Paul A
Harness & Dickey & Pierce P.L.C.
Jackson, Jr. Jerome
Samsung Electronics Co,. Ltd.
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