Semiconductor memory device and method of controlling timing

Details Semiconductor memory device and method of controlling timing Semiconductor memory device and method of controlling timing

2007-09-25

2009-08-04

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S191000, C365S210120, C365S210130, C365S233100

Reexamination Certificate

active

07570531

ABSTRACT:
In a semiconductor memory device, in addition to a sense amplifier connected to bit lines of a memory cell array having a plurality of memory cells in a disconnectable manner, the sense amplifier performing confinement operation to disconnect the bit lines of the memory cell array and amplify a data signal during data sense operation from the memory cells, there is provided a timing adjustment circuit adjusting timing related to confinement operation in the sense amplifier, so as to allow adjusting of timing of the confinement operation and setting of timing of the confinement operation.

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