Semiconductor memory device and method of controlling the same

Details Semiconductor memory device and method of controlling the same Semiconductor memory device and method of controlling the same

2003-10-29

2004-11-02

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C365S189040, C365S189050, C365S201000, C365S220000, C365S221000, C365S236000

Reexamination Certificate

active

06813696

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device in synchronization with an external clock signal and its control method, and relates in particular to synchronous DRAM (Synchronous Dynamic Random Access Memory: SDRAM) which reads or writes data synchronously with the external clock signal and its control method for writing data.
2. Description of the Related Art
The conventional DRAM inputs or outputs data independently (Asynchronous) from the clock signal supplied to a system, thereby preventing the input of following addresses until the data corresponding to the address is output from an address input. Thus the cycle time of a data transfer depends upon the access time up to the data output, thus causing a difficulty in the improvement of data transfer rate. For this reason, along with a remarkable improvement of processing speed of a processing unit (MPU) installed in the personal computer (PC) in recent years, the improvement of the data transfer speed of the DRAM used as a main memory in the PC arises as an important object.
To address this problem, a SDRAM with the column access path divided into several pipelines and the read/write process between each pipelines synchronized with the rising edge of the external clock signal supplied from the system side has been developed. Furthermore, with no change in the basic architecture of the circuit, a SDRAM in DDR mode (Double Data Rate) which inputs or outputs the data synchronously with both the rising and falling edges of the external clock signal (CLK) is developed (for example, described in particular in Japanese Application No. 9-167451, Japanese Application No. 10-22257, etc.) The data transfer rate of the SDRAM in the DDR mode has an advantage of being approximately twice as fast as that of the SDRAM in which the data is synchronized in transmission only with the rising edge of the external clock signal (hereinafter called SDR mode for convenience), thus becoming the present mainstream of the SDRAM.
SUMMARY OF THE INVENTION
Now, these semiconductor memory devices are tested and evaluated by memory test equipment (IC tester) in the manufacturing stage. The memory test equipment's functions include counting the number of defective memory cells and judging whether the repair of the defective memory cells is feasible under a situation identical to the normal operative condition. For example, in testing for the defective memory cells in the SDRAM, the memory test equipment generates a signal identical to the external clock signal CLK used during the actual operation of the SDRAM and input it to the SDRAM. It should be noted that a wafer test checks all chips formed on a semiconductor wafer and tests writing and reading of the predetermined data to each chip.
However, the above-mentioned SDRAM having the DDR mode is quite different from the SDRAM having the conventional SDR mode in operations. Especially in the write/read operation, since the DDR mode generates the write/read data in frequency twice that of the conventional type, it is required to newly introduce the memory test equipment which can generate the clock signal for a test corresponding to the DDR mode. This in turn requires the purchase of new memory test equipment for manufacturing SDRAM in the DDR mode, so resulting in higher investment in equipment and increasing the cost of the SDRAM having the DDR mode. Also, the inability of using the conventional memory test equipment causes a delay in product development of the DDR mode SDRAM.
More specifically, there is a restriction that only one strobe can be generated within one clock in the semiconductor tester. When the SDRAM is tested with DDR method under such restriction, two outputs are provided in one clock, requiring the use of two clocks from the semiconductor tester as one clock and to generate two strobes within one clock of clocks given to the semiconductor memory device. That is, the test must be executed by operating the semiconductor memory device in half the frequency of the actual tester ability.
FIG. 21
is a timing chart showing a comparison between the data reading tests in the wafer test of the semiconductor memory device regarding to an embodiment of the prior and present inventions.
FIG. 22
is a timing chart showing a comparison between the data writing tests in the wafer test of the semiconductor memory device regarding to an embodiment of the prior and present inventions. Here, FIG.
21
(
a
) and FIG.
22
(
a
) are the timing charts of the data reading and data writing tests of the SDRAM in the DDR type which is a conventional semiconductor memory device, and FIG.
21
(
b
) and FIG.
22
(
b
) are the timing charts of the data reading and data writing tests of the SDRAM of the DDR type which is a semiconductor memory device as an embodiment of the present invention later described.
As shown in FIG.
21
(
a
), since the conventional data reading test in the wafer test of the SDRAM having the DDR type can execute only the reading operation in the DDR type, it, for example, gives a clock (a device clock) CLK which has a cycle (T=2xt) twice as long as the main clock (a tester clock) clk of the semiconductor tester to the SDRAM in the DDR type to read twice standing two strobes (STB) to one clock of this device clock CLK. Here, when a CAS latency is 1.5 clocks (CL=1.5) and a bus length is 8 (BL=8: when 8 different data are read), the completion of a series of data readings requires a time equivalent to 13 clk's after an active state.
Also, as shown in FIG.
22
(
a
), the conventional data writing test in the wafer test of the SDRAM having the DDR type allows only the write operation in the DDR type, therefore, for example, two write operations are executed during one clock of this device clock CLK by giving a device clock CLK which has a cycle (T=2xt) twice as long as that of the tester clock clk. Here, When the 8 different data are written by delayed write, the completion of a series of write operations requires a time equivalent to 13 clk's (tester clocks) after active state.
By the way, since the wafer test is required for all chips formed on the semiconductor wafer, testing by operating the device with a half the frequency of the actual semiconductor tester like this leads to a problem to introduce an increase in manufacturing cost. For example, testing the SDRAM of the DDR type under the ordinary operation requires expensive test equipment that has a frequency band twice as fast as the operation speed of the SDRAM, which consequently increases the manufacturing cost of the SDRAM of the DDR type significantly. Use of the ordinary test equipment, on the other hand, requires all device clocks CLK to be operated with a half the frequency of the tester clock clk and a redundant timing must be set in all tests. Consequently, the test time becomes longer and also the manufacturing cost of the devices is increased.
An object of the present invention is to provide a semiconductor memory device that can be easily tested and evaluated by the conventional memory test equipment and its control method, while having a transfer mode to transfer data in synchronization with the rising and falling edges of the external clock.
A further object of the present invention is to provide a semiconductor memory device that can reduce the test time without the use of expensive test equipment.
The above objects are achieved by a semiconductor memory device operable in synchronization with an external clock signal, comprising a data transfer circuit, having a first transfer mode and a second transfer mode, for transferring data in synchronization with rising and falling edges of an external clock signal in the first transfer mode, and for transferring data in synchronization with only one of the rising and falling edges in the second transfer mode. Also, in the semiconductor memory device of the present invention, the data transfer circuit switches the first and second transfer modes in response to a mode switc

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