Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2003-04-23
2004-05-25
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S226000
Reexamination Certificate
active
06741514
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor memory device and a method of controlling the same, and particularly relates to a semiconductor memory device which needs a refresh operation and a method of controlling the same.
BACKGROUND ART
As shown in
FIG. 2
, a semiconductor memory device such as a DRAM needs to perform a refresh operation in order to store data by accumulating electric charge in a capacitor element
21
in a memory cell and hold the electric charge. In this refresh operation, the potential of the capacitor element
21
in the memory cell is taken out to a bit line BL, and the potential difference between bit lines BL and /BL is amplified by a sense amplifier
17
. Here, “/” means a bar indicating a logical inversion signal and hereinafter it is used in the same sense. To increase the speed of this amplification, the aforementioned amplification of potential difference is performed by the use of a first power source Vdd which is higher than a second power source Vii.
FIG. 12
is a timing chart showing a method of controlling a semiconductor memory device (DRAM) according to a prior art. When a word line WL is changed from a low level to a high level, a slight difference occurs between bit lines BL and BLs, and /BL and /BLs according to the electric charge accumulated in the capacitor element
21
. The sense amplifier
17
amplifiers this potential difference after a timing t1.
Next, the control method at the timing t1 will be explained. By changing a second sense amplifier activating signal line LEz from a low level to a high level, an n-channel MOS transistor
16
(
FIG. 2
) is turned on. By changing an overdrive signal line LEPx from a high level to a low level, a p-channel MOS transistor Q
1
is turned on. By maintaining a first sense amplifier activating signal line LEx at a high level, a p-channel MOS transistor Q
2
remains off. Hence, a node PSA is connected to the first power source VDD, and a node NSA is connected to a potential Vss (ground). For example, the bit lines BL and BLs are amplified toward the potential of the first power source Vdd, and the bit lines /BL and /BLs are amplified toward the potential Vss.
Next, the control method at a timing t2 will be explained. By maintaining the second sense amplifier activating signal line LEz at the high level, the n-channel MOS transistor
16
remains on. By changing the overdrive signal line LEPx from the low level to the high level, the p-channel MOS transistor Q
1
is turned off. By changing the first sense amplifier activating signal line LEx from the high level to a low level, the p-channel MOS transistor Q
2
is turned on. Hence, the node PSA is connected to the second power source Vii, and the node NSA is connected to the potential Vss. For example, the bit lines BL and BLs are amplified toward the potential of the second power source Vii, and the bit lines /BL and /BLs are amplified toward the potential Vss.
The potential of a cell node (storage node) CN after t1 changes according to the potential of the bit line BLs. A data amplification time T3 is the time from the timing t1 until the potential of the cell node CN reaches the potential of the second power source Vii.
As described above, between the timings t1 and t2, the amplification is performed by the high power source Vdd, and after the timing t2, the amplification is performed by the low power source Vii. The aforementioned transient supply of the high power source Vdd to a sense amplifier is called overdrive, and this type of sense amplifier is called an overdrive sense amplifier. The data amplification time T3 can be shortened more by using two power sources Vdd and Vii than by using one power source Vii.
As shown in
FIG. 12
, the potential of the cell node CN after t1 changes later than the potential of the bit line BLs. To shorten the data amplification time T3, it is thought to raise the potential of the bit line BLs to a potential higher than the potential of the power source Vii for maintaining the potential of the memory cell. However, since the potential of the bit line BLs is thereafter stabilized at the potential of the power source Vii, it is required to switch the power source from Vdd to Vii. On this occasion, excess potential over the potential Vii of the bit line BLs needs to be extracted by the power source Vii. A current for extracting the excess potential is a wasteful current, and thus power consumption unnecessarily increases. Moreover, variations occur to the data amplification time T3 due to manufacturing variability in semiconductor memory devices or operating environment.
An object of the present invention is to provide a semiconductor memory device including a sense amplifier capable of amplifying data in a memory cell at high speed and with low power consumption and a method of controlling the same.
Another object of the present invention is to provide a semiconductor memory device including a sense amplifier capable of preventing variations in data amplification time due to manufacturing variability and a method of controlling the same.
Still another object of the present invention is to provide a semiconductor memory device including a sense amplifier capable of preventing variations in data amplification time due to changes in environment such as temperature and a method of controlling the same.
SUMMARY OF THE INVENTION
A semiconductor memory device of the present invention comprises a memory cell array in which a plurality of memory cells for storing data are arranged, a sense amplifier for amplifying the data in the memory cell, a first power source, and a second power source lower than the first power source. In a first step, the sense amplifier receives power supply from the first power source to amplify the data in the memory cell. In a second step, the sense amplifier does not receive power supply either from the first power source or from the second power source. In a third step, the sense amplifier receives power supply from the second power source to amplify the data in the memory cell.
By supplying the first high power source to the sense amplifier in the first step, the potential of a bit line connected to an output of the sense amplifier can be made higher than the potential of the second low power source, and hence the data in the memory cell can be amplified at high speed. By not supplying either the first power source or the second power source to the sense amplifier in the second step, the potential of the bit line, which is made higher than the potential of the second low power source, can be lowered by charging the cell and an end of the bit line, and hence power consumption can be reduced without electric power being consumed wastefully. By supplying the second low power source to the sense amplifier in the third step, the memory cell can be stabilized at a predetermined maintenance potential.
REFERENCES:
patent: 5726943 (1998-03-01), Yamagata et al.
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patent: 10-269771 (1998-10-01), None
patent: 10-302467 (1998-11-01), None
patent: 11-273357 (1999-10-01), None
patent: 2000-285676 (2000-10-01), None
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