Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-04-20
2011-11-29
Trimmings, John (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S006240, C714S746000, C714S751000, C714S752000, C714S755000, C714S777000, C714S818000, C365S185010, C365S185090, C365S185330
Reexamination Certificate
active
08069394
ABSTRACT:
A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
REFERENCES:
patent: 5734663 (1998-03-01), Eggenberger
patent: 6941505 (2005-09-01), Yada et al.
patent: 7239547 (2007-07-01), Suda
patent: 7551478 (2009-06-01), Kanno
patent: 7590919 (2009-09-01), Kanno
patent: 7900117 (2011-03-01), Kanno
patent: 2005/0172207 (2005-08-01), Radke et al.
patent: 2005/0210361 (2005-09-01), Nagai
patent: 2007/0130496 (2007-06-01), Kanno
patent: 2007/0157064 (2007-07-01), Falik et al.
patent: 2007/0174740 (2007-07-01), Kanno
patent: 2007/0226588 (2007-09-01), Lee et al.
patent: 2008/0163023 (2008-07-01), Hong et al.
patent: 2008/0168319 (2008-07-01), Lee et al.
patent: 2009/0013233 (2009-01-01), Radke
patent: 2009/0100307 (2009-04-01), Lee
patent: 2009/0150749 (2009-06-01), Kim et al.
patent: 2009/0241010 (2009-09-01), Yano et al.
patent: 2009/0327604 (2009-12-01), Sato et al.
patent: 2009/0327802 (2009-12-01), Fukutomi et al.
patent: 2009/0327803 (2009-12-01), Fukutomi et al.
patent: 2010/0005228 (2010-01-01), Fukutomi et al.
patent: 2010/0161885 (2010-06-01), Kanno et al.
patent: 2010/0205509 (2010-08-01), Kirschner et al.
patent: 2010/0223531 (2010-09-01), Fukutomi et al.
patent: 2010/0262889 (2010-10-01), Bains
patent: 0 176 218 (1986-04-01), None
patent: 63-275225 (1988-11-01), None
patent: 07-248930 (1995-09-01), None
patent: 10-97471 (1998-04-01), None
patent: 2000-101447 (2000-04-01), None
patent: 2000-181807 (2000-06-01), None
patent: 2000-269824 (2000-09-01), None
patent: 2003-196165 (2003-07-01), None
patent: 2004-501466 (2004-01-01), None
patent: 2005-216437 (2005-08-01), None
patent: 2007-299449 (2007-11-01), None
patent: 2000-9059422 (2009-03-01), None
patent: 2009-080651 (2009-04-01), None
patent: 2009-211742 (2009-09-01), None
patent: 2010-238363 (2010-10-01), None
patent: WO 01/98872 (2001-12-01), None
patent: WO 01/98872 (2001-12-01), None
patent: WO 2007/036834 (2007-04-01), None
Kanno Shin-ichi
Uchikawa Hironori
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Trimmings John
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