Semiconductor memory device and method of changing output...

Details Semiconductor memory device and method of changing output... Semiconductor memory device and method of changing output...

2001-03-27

2001-10-30

Fears, Terrell W. (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S189050, C365S230080

Reexamination Certificate

active

06310818

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having multiple ports.
A multiport memory and a delay line constitute a semiconductor memory device that has multiple ports. A multiport memory includes a plurality of address and input/output (I/O) circuits, and is used to transfer messages between processors. A delay line includes a data input circuit and a data output circuit, and is used to process images.
In some of the multiple-port semiconductor memory devices, when write data is provided to a memory cell from one of the ports, the write data is used to change read data, which has been read from the memory cell by a read circuit.
FIG. 1
is a schematic block diagram of a prior art multiport memory
10
. The multiport memory
10
includes a memory cell array
11
, a data write circuit
13
, a data read circuit
14
, an address comparison circuit
15
, a write detection circuit
16
, a data changing circuit
17
, port A and port B (not shown). The memory cell array
11
includes memory cells
12
, which are arranged in a matrix-like manner. The multiport memory
10
writes data (write data) WD that is input through the port A to the memory cells
12
, and outputs data (read data) RD that is read from the memory cells
12
via the port B.
The data write circuit
13
drives a pair of first bit lines BLA, XBLA based on the write data WD. A row decoder (not shown) drives first word lines WLA. The memory cells
12
are each connected to one of the first word lines WLA and stores data (memory information) based on the potential at the pair of first bit lines BLA, XBLA. Further, the row decoder drives second word lines WLB to read the information stored in the memory cells
12
into a pair of second bit lines BLB, XBLB.
The data read circuit
14
includes a sense amplifier and a latch circuit. The sense amplifier amplifies the potential difference between the second bit lines BLB, XBLB and generates amplified data. The potential difference is generated in correspondence with the information stored in the memory cells
12
. The latch circuit latches the amplified data and generates a single bit of read data, and subsequently outputs the read data RD to an external device. The sense amplifier ceases functioning when the latch circuit latches the amplified data.
The address comparison circuit
15
, the write detection circuit
16
, and the data changing circuit
17
changes read data RD that is read into the port B with write data WD that is newly written to the memory cells
12
via the port A. The write data WD is stored at the same address as the read data RD.
The address comparison circuit
15
compares a write address with a read address to generate a comparison signal S
1
and provide the comparison signal S
1
to the data changing circuit
17
. The write detection circuit
16
detects whether data is written to other ports (e.g., the port A in FIG.
1
), generates a detection signal S
2
and provides the detection signal S
2
to the data changing circuit
17
.
The data changing circuit
17
generates an activation signal S
3
based on the comparison and detection signals S
1
, S
2
. The data changing circuit
17
generates the activation signal S
3
when the write address and the read address are the same and data is written to port A. The sense amplifier of the data read circuit
14
is activated based on the activation signal S
3
.
When the write address and the read address are the same, the first and second word lines WLA, WLB connected to the memory cell
12
(into which the write data WD is to be written) are both activated. Accordingly, the potential difference generated between the second bit lines BLB, XBLB is equal to the potential difference between the first bit lines BLA, XBLA, or the potential difference corresponding to the write data WD. In this state, the sense amplifier amplifies the potential difference between the second bit lines BLB, XBLB. Accordingly, the latch circuit latches a signal having the same value as the write data WD to generate the read data RD.
It is increasingly desirable for semiconductor memory devices to have higher integration capabilities and higher operating speeds. If the number of ports is increased in order to operate a multiport memory at a higher speed, the number of the address comparison circuit
15
, the write detection circuit
16
, and the data changing circuit
17
will increase accordingly. An increase in the number of the circuits
15
,
16
,
17
results in an increase in the chip area and thereby hinders the integration capability of the semiconductor memory device.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a multiple-port semiconductor memory device that enables higher integration and a method for changing output data in such a semiconductor memory device.
To achieve the above object, the present invention provides a method for changing output data of a semiconductor memory device having a plurality of ports. The semiconductor memory device includes a plurality of memory cells, a first bit line connected to the memory cells, a second bit line connected to the memory cells, a first port connected to the first bit line for writing input data to the memory cells via the first bit line, a second port connected to the second bit line for outputting data stored in the memory cells via the second bit line, and a data read circuit connected to the second bit line and having a latch circuit for holding the data of one of the memory cells. The method includes detecting a change in the stored data of the memory cell based on a potential at the second bit line, and changing the data held at the latch circuit when a change in the stored data is detected.
The present invention further provides a semiconductor memory device including a plurality of memory cells, a first word line connected to the memory cells, a second word line connected to the memory cells, a first bit line connected to the memory cells, and a second bit line connected to the memory cells. A first port is connected to the first word line and the first bit line for writing input data into the memory cells via the first bit line by activating the first word line. A second port is connected to the second word line and the second bit line for outputting data stored in each of the memory cells via the second bit line by activating the second word line. The second port includes a data read circuit connected to the second bit line for receiving the stored data and generating output data from the stored data. A data holding circuit is connected to the data read circuit for holding the output data and generating holding data. A data change detection circuit is connected to the second bit line for detecting whether the stored data has changed based on a potential at the second bit line. A data changing circuit is connected to the data change detection circuit and the data holding circuit for changing the output data using the holding data.
The present invention further provides a delay line including a plurality of memory cells, a first word line connected to the memory cells, a second word line connected to the memory cells, a first bit line connected to the memory cells, and a second bit line connected to the memory cells. A first port is connected to the first word line and the first bit line for writing input data to the memory cells via the first bit line by activating the first word line. A second port is connected to the second word line and the second bit line for outputting data stored in each of the memory cells via the second bit line by activating the second word line. The second port includes a data read circuit connected to the second bit line for receiving the stored data and generating output data from the stored data. A data holding circuit is connected to the data read circuit for holding the output data and generating holding data. A data change detection circuit is connected to the second bit line for detecting whether the

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