Semiconductor memory device and method of arranging a...

Details Semiconductor memory device and method of arranging a... Semiconductor memory device and method of arranging a...

2008-04-01

2008-04-01

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S185210, C365S196000, C365S207000

Reexamination Certificate

active

07352646

ABSTRACT:
A semiconductor memory device with improved operational performance by reducing the level variation of first and second power voltages applied to a sense amplifier by efficiently locating a decoupling capacitor. The decoupling capacitor is arranged on an empty region of a plurality of the first and second sense amplifiers and connected between the first and second power voltage lines. A plurality of global data I/O line pairs is arranged perpendicular to the direction of a plurality of local data I/O line pairs.

REFERENCES:
patent: 5311478 (1994-05-01), Zagar et al.
patent: 5594704 (1997-01-01), Konishi et al.
patent: 6222223 (2001-04-01), Tobita
patent: 6337824 (2002-01-01), Kono et al.
patent: 6392942 (2002-05-01), Noda et al.
patent: 6392944 (2002-05-01), Kono
patent: 6674676 (2004-01-01), Hsu et al.
patent: 2003-0001242 (2003-01-01), None
English language abstract of Korean Publication No. 2003-0001242.

Affiliated with

Also associated with

Rating

Semiconductor memory device and method of arranging a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device and method of arranging a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and method of arranging a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2774730