Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2002-07-19
2003-10-28
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S201000, C365S200000
Reexamination Certificate
active
06639848
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-221920, filed Jul. 23, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and to a semiconductor memory device allowing a redundancy circuit replacement on an electrically programmable nonvolatile memory element and a method for testing the same and, in particular, this enables the replacement of the redundancy circuit to be programmed while being in a parallel testing state in an die-sort test.
2. Description of the Related Art
In a semiconductor memory such as a DRAM, a die-sorting test (hereinafter referred to as a DS test) is made by a tester before a shipment to detect any fail chip. The DS test comprises a DC test for monitoring electric current and voltage or an AC test for confirming a basic read/write operation by varying the test pattern and voltage, and so on. In this DS test, a parallel testing is carried out so as to shorten a normal testing time.
The “parallel testing” means testing a plurality of chips by the same DS tester at a time in a parallel state on one wafer. In this case, it is only possible to apply all the same voltage waveform, including a timing, to the same signal pad of respective chips. Stated in more detail, when a voltage waveform of, for example, a high level → a low level → a high level (here, a high level is referred to as a “H” level and a low level as a “L” level) is applied to a /RAS pad of a specified chip, al the same voltage waveform is applied also to a /RAS pad of another chip.
After the ending of the DS test, whether each chip including any fail bit is retrievable (pass) or not (fail) by a redundancy circuit replacement is decided based a fail bit address detected by the test and this decision is so done under a software using any calculation algorithm.
The redundancy circuit replacement has now been extensively utilized in the field of the semiconductor memory and any fail memory cell can be retrieved through the redundancy cell replacement, thus achieving an improved yield. Normally, a plurality of rows or columns in the memory cell array are set as a cell array unit for retrieval and any defect-detected cell array unit is replaced by a redundancy cell (spare element) unit of the same size.
If, therefore, any defect bit containing unit so detected by the DS test is replaceable all with the redundancy circuit, its chip is “passed” while, on the other hand, if it is not replaceable, its chip “fails”. For only the chip decided as being “passed”, the redundancy circuit replacement is programmed in a hardware way.
Those programmed contents are address information of a defect-containing cell array unit to be replaced with a redundancy cell array unit. For the storage of such information it is necessary to use a nonvolatile memory element. A laser fuse is now commonly used for a program to allow a connection line to be blown with a laser irradiation from a laser blowing machine and, as its material, use is made of a metal, a polysilicon and so on.
With a large increase in the memory capacity, a total number of such laser fuses are inevitably increased and, since the pitch (the size of one fuse and its adjacent fuse interval) of fuses is determined by the performance of the laser blowing machine, it has been difficult to follow the scaling of the design rules for miniaturization. And a relative occupation percentage of such laser fuses in a chip becomes greater.
One solution to this problem is by replacing a conventional laser fuse with an electrically programmable fuse (here referred to as an EFUSE) or a nonvolatile semiconductor memory element. Here, the EFUSE is comprised of a fuse programmed by electrically short- or open-circuiting the connection line, etc., formed of a capacitor's insulating film, a metal and a polysilicon by the application of a voltage or current.
As one example, an EFUSE is listed here which is programmed by applying high voltage to a capacitor's insulating film in a DRAM cell to cause it to be broken down and thus cause it to be electrically short-circuited. Further, here, the nonvolatile semiconductor memory element generally means a flash memory, an EEPROM, an FeRAM (Ferroelectric RAM), an MRAM (Magnetic RAM) cell, etc., serving as a nonvolatile semiconductor memory having a read, a write and a data hold function. Here, for convenience's sake, the EFUSE and nonvolatile semiconductor memory element, together, are called as an electrically programmable nonvolatile memory element.
In the EFUSE programmed by breaking down the capacitor's insulating film of the DRAM cell, for example, it follows that, with the miniaturization of the semiconductor memory, the EFUSE section is correspondingly scaled down. It is, therefore, possible to reduce the occupation area of a chip compared with that of the laser fuse. Further it is also possible to secure a fail bit retrieval after a burn-in testing (after a package sealing).
It is considered that, in the future, the redundancy circuit replacement fuse will be wholly replaced with the electrically programmable nonvolatile memory element in place of the now generally used laser fuse. Here, a problem lies in how to reduce a time necessary for such programming and hence reduce a testing time and cost when a program operation is applied to an electrically programmable nonvolatile memory element.
In general, the electrically programmable nonvolatile memory element can be used to store address information of a cell array unit including a defect. As an example using an EFUSE to store the address information, an explanation will be made below in more detail about the conventional program operation.
A test flow for the conventional redundancy circuit replacement will be explained below by referring to FIG.
1
.
In the ending of a wafer process S
101
, a resultant memory wafer is shifted to a DS test. In the DS test S
102
, checking is made, by the DS tester, for any defect chip in a parallel testing so as to enhance the test efficiency. Whether any defect chip is retrievable or not with a redundancy circuit replacement is decided based on a defect bit included in a defect chip detected by the DS tester in the parallel testing state. If the defect chip is decided as being retrievable, shifting is made to an EFUSE blowing step S
103
for the redundancy circuit replacement. Here the “blowing” means the operation of programming a fuse.
In the parallel testing state, however, a plurality of chips are tested in parallel by the same DS tester at a time and all the same voltage waveform including a timing is applied to the same signal pad of the respective chip. It is, therefore, not possible to execute any redundancy circuit replacement program on the defect chip only by directly using the DS tester in a parallel testing state.
It is, therefore, necessary to again test a plurality of chips in a parallel testing state one by one by another tester and execute a redundancy circuit replacement program for any defect chip. This method takes a longer time for the redundancy circuit replacement and involves a rise in a testing cost.
With reference to
FIG. 2
an explanation will be made below about a conventional main circuit arrangement in the case of using the EFUSE for the redundancy circuit replacement.
(1) EFUSE Programming Operation
As shown in
FIG. 2
, an EFUSE program control circuit
101
receives a clock signal CLK
2
and a program signal TM_PROG and outputs a plurality of control signals S_
1
, . . . , for the EFUSE program operation.
An EFUSE circuit
102
for executing the EFUSE program operation is controlled with the use of the plurality of control signals S_
1
, S_
2
, S_
3
, S_
4
and S_
5
and the EFUSE program operation is executed by applying a program pulse (voltage VBP) to an address-selected EFUSE.
(2) EFUSE Read Operation
In the EFUSE read operation, th
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Phung Anh
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