Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2003-08-04
2004-11-02
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S222000, C365S189080, C365S233500, C365S194000, C365S195000
Reexamination Certificate
active
06813203
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2002-231645, filed on Aug. 8, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a method for testing a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having functions for processing external and internal accesses, and to a method for testing such a semiconductor memory device.
Electronic information devices incorporate semiconductor memory devices having large memory capacities (i.e., dynamic random access memory (DRAM)). A DRAM has a self-refreshing function to refresh the data of a memory cell in accordance with a counting operation performed by an internal circuit. The DRAM does not require an external device to perform refreshing. This decreases power consumption and simplifies the design of circuits in the periphery of the DRAM.
In a DRAM provided with the self-refreshing function, a timer of an internal circuit generates refresh requests (internal access) at predetermined time intervals. Further, a main controller of an external device generates write/read requests (external access) at certain timings. In other words, internal and external accesses are generated asynchronously. Accordingly, there is a demand for evaluating a DRAM having two asynchronous access modes.
FIG. 1
is a schematic block circuit diagram illustrating the input section of a prior art semiconductor memory device (DRAM)
50
provided with a self-refreshing function.
The DRAM
50
receives a plurality of control signals CTL and a plurality (only two bits shown in
FIG. 1
) of external address signals ADD via external terminals. The control signals CTL include a chip enable signal /CE, a write enable signal /WE, and an output enable signal /OE. The external address signals ADD include address signals A
0
and A
1
. The signals /CE, /WE, /OE, A
0
, and A
1
are input to a transition detection signal generation circuit
70
via input buffers
61
,
62
,
63
,
64
, and
65
, respectively. The input buffers
61
to
65
function as initial input stage circuits, which convert an input signal to a signal having a level corresponding to the internal voltage of the device. Further, the input buffers
61
to
65
are each configured by a CMOS inverter or a C/M differential-amplifier.
The transition detection signal generation circuit
70
includes a plurality (five in
FIG. 1
) of transition detectors (TD)
71
to
75
and a pulse synthesizing circuit
76
.
The transition detectors
71
,
72
, and
73
respectively detect the transition (transition between a high level and a low level) of the control signals CTL (/CE, /WE, and /OE) to generate input detection signals ceb, web, and oeb. The transition detectors
74
and
75
respectively detect the transition of the states (change of each bit) of the input external address signal ADD (A
0
and A
1
) to generate address detection signals ad
0
and ad
1
. The detection signals ceb, web, oeb, ad
0
, and ad
1
are provided to the pulse synthesizing circuit
76
.
The pulse synthesizing circuit
76
generates a transition detection signal mtd in accordance with the detection signals ceb, web, oeb, ad
0
, and ad
1
and provides the transition detection signal mtd to a memory control circuit
77
. In accordance with the transition detection signal mtd, the memory control circuit
77
generates a word line activation timing signal wl-timing to activate a word line of a memory cell. The word line of a memory cell corresponds to a predetermined read/write address, which is assigned by the external address signal ADD. The timing signal wl-timing is provided to a memory core
79
.
A refresh timer
78
is connected to the memory control circuit
77
. The refresh timer
78
generates a refresh request signal ref-req at predetermined time intervals and provides the refresh request signal ref-req to the memory control circuit
77
. In accordance with the refresh request signal ref-req, the memory control circuit
77
generates a word line activation timing signal wl-timing to activate a word line of a memory cell. The word line of a memory cell corresponds to a predetermined refresh address, which is generated by an internal address counter (not shown).
The memory control circuit
77
further receives a test signal test from a test circuit (not shown) to conduct a test in a test mode in accordance with the test signal test.
FIG. 2
is a schematic block circuit diagram of the memory control circuit
77
. The memory control circuit
77
includes a refresh determination circuit
81
, an internal command generation circuit
82
, and a timing generator
83
.
The refresh determination circuit
81
receives the transition detection signal mtd, the refresh request signal ref-req, and the test signal test. In response to the refresh request signal ref-req, the refresh determination circuit
81
generates a refresh start signal ref-start, which starts refreshing (internal access), and a refresh state signal ref-state. The refresh start signal ref-start is provided to the timing generator
83
, and the refresh state signal ref-state is provided to the internal command generation circuit
82
.
When receiving the transition detection signal mtd before the refresh request signal ref-req, the refresh determination circuit
81
suspends refreshing and does not generate a refresh signal.
In this state, the refresh determination circuit
81
gives priority to read/write operations (external accesses) and starts refreshing after the read/write operations are completed. More specifically, after a read/write state signal rw-state, which is provided from the timing generator
83
, is reset, the refresh determination circuit
81
generates the refresh start signal ref-start and the refresh state signal ref-state.
The refresh determination circuit
81
determines the input timings of the refresh request signal ref-req and the transition detection signal mtd, which are asynchronously input, and determines which one of the refreshing operation and the read/write operation has priority when there is more than one access.
In response to the transition detection signal mtd, the internal command generation circuit
82
generates the read/write start signal rw-start, which starts read/write operations, and provides the read/write start signal rw-start to the timing generator
83
. When the internal command generation circuit
82
receives the refresh state signal ref-state, the internal command generation circuit
82
provides the read/write start signal rw-start to the timing generator
83
after the refresh state signal ref-state is reset.
The timing generator
83
receives the refresh start signal ref-start and the read/write start signal rw-start. In response to the refresh start signal ref-start, the timing generator
83
generates the word-line activation timing signal wl-timing in correspondence with the refresh address. In response to the read/write start signal rw-start, the timing generator
83
generates the read/write state signal rw-state and generates the word-line activation timing signal wl-timing in correspondence with the predetermined read/write address.
In addition to the word line activation timing signal wl-timing, the timing generator
83
generates other internal operation signals, such as a sense amplifier activation timing signal for activating a sense amplifier. Only the word line activation timing signal wl-timing will be discussed below.
The operation of the DRAM
50
will now be discussed.
FIG. 3
is a waveform diagram illustrating the operation of the transition detection signal generation circuit
70
.
For example, when the chip enable signal /CE goes low, the transition detector
71
generates the input detection signal ceb (pulse signal). The pulse synthesizing circuit
76
generates the transition detection signal mtd in accordance with the transition si
Arent & Fox PLLC
Fujitsu Limited
Tran Andrew Q.
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