Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-09-27
2003-09-09
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S230030, C365S230060, C365S185200
Reexamination Certificate
active
06618300
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention broadly relates to a semiconductor memory device, and a method for replacing a redundant circuit. More specifically, this invention is directed to a semiconductor memory device which has an improved redundant subword selection circuit in a subword system.
With recent reduction of a semiconductor device in size, an LSI (Large scale integrated circuit) having the semiconductor device has become popular.
For example, a dynamic type random access memory (DRAM) or a synchronous random access memory (SDRAM) has been used as a semiconductor memory device having capacity of 256 Mbit for one chip.
In such a semiconductor memory device, a memory cell array is divided into a plurality of banks. With this structure, a redundant memory cell array, namely, a redundant memory region is provided outside a main memory in each bank.
Herein, a normal memory cell array is arranged in the main memory while a spare memory cell array is placed in the redundant memory cell array.
Meanwhile, suggestions have been made in the art about a word shunt system with respect to word line selection for selecting a predetermined memory cell.
In such a word shunt system, a gate wiring pattern (wiring line) and a metal pattern (metal line) having low resistance are alternately wired in parallel as a wiring method for improving writing/reading speed.
However, it is becoming difficult to form a metal wiring layer for the word shunt in accordance with the pitch of the memory cell with large capacity memory.
To solve this problem, use generally has been made of a subword system in which a subword driver is arranged in the memory cell array so as to designate via the subword driver.
In the above-discussed semiconductor memory device of the sub-word system, application has been made about a defect relieving technique in which a spare redundant memory cell array is used instead of the defective memory when a defect is detected in a part of the main memory.
In other words, even when a small number of defects occur in the main memory region in a production process, the total function of the semiconductor memory device will not be damaged.
In such a semiconductor memory device having a redundant circuit, an electrical characteristic test is carried out in a wafer-selecting step during the production process.
As the result of the test, when the defect exists in the memory cell array, the address of the memory cell array having the defect is programmed with a fuse arranged inside the redundant circuit.
Thereby, the writing/reading operation is halted for a defective memory cell in the main memory region, and the writing/reading operation is performed by the redundant memory cell in the redundant memory region.
In this event, the switching to the redundant memory cell is carried out at every word line and every bit line. Under this circumstance, address information of the defective portion is necessary in the switching for each word line while bit position information of the defective portion is required for each bit line.
Namely, when the defective memory cell is detected, the position of the fuse to be cut is determined on the basis of the address information of the defective portion, and the fuse is, for example, fused by irradiating it with a laser beam. With this fusing, the position of the defective memory cell is written to a ROM fuse.
As described above, the position of the defective memory cell is written to the fused ROM. Consequently, when the memory corresponding to the cut fuse is selected, the switching is carried out such that the redundant memory region is selected in lieu of the main memory.
More specifically, the address of the memory cell in the selected main memory region is compared with the address of the defective memory cell in the redundant memory region. In the comparison result, if the defective memory cell is selected, the redundant memory cell in the redundant memory region will be accessed.
As discussed before, the number of necessary redundant memory cells is also increased with the increase of the memory capacity of the semiconductor memory device.
Accordingly, it is important to reduce the number of component elements of the semiconductor memory device as small as possible in order to efficiently arrange the increased number of redundant memory cells.
Referring to
FIG. 1
, a related memory cell array will now be described.
Such a memory cell array is divided into two banks, an A bank and a B bank in an X-direction (a lateral direction), and is divided into two banks in a Y-direction (a vertical direction). Thereby, the memory cell array is divided into four areas consisting of an upper bank A, a lower bank A, an upper bank B, and a lower bank B.
With such a structure, one bank, for example, the A bank, has a memory capacity of 32 M bits, and is further divided into 16 plates of A
0
P~A
15
P. Each of the plates A
0
P and A
1
P is composed of one plate. The one plate (a portion indicated by oblique lines in the figure) has 2M bits, and 512 word lines×4K bit lines. In the 512 word lines, the address is composed of 9 bits of X
0
~X
8
.
A word driver block
11
is arranged in the X-direction, and a driving word line is lined up although not shown. Further, a bit line is arranged so as to cross with a main word line extended in the Y-direction from the word driver block, although also not shown.
The selection of the memory cell is carried out by selecting the word line arranged in the X-direction by the use of the X-address and by selecting the bit line arranged in the Y direction by the use of the Y address.
Under this circumstance, a data signal is written/read for the selected memory cell by selecting the memory cell positioned at the portion where the word line and the bit line are crossing.
In the above-mentioned semiconductor memory device, the word driver for driving the word line of the memory cell array is connected to a backed metal wiring pattern (line) such as an aluminum pattern in the output thereof, and is constituted with the same pitch as the polysilicon wiring pattern and the aluminum wiring pattern.
However, the reduction in size has advanced with the large capacity of the LSI, as described above. In consequence, it is becoming difficult to pattern the aluminum line with the pitch of the polysilicon wiring line connected to the gate of the memory cell.
Further, the height of the formation layer in a memory cell portion on a semiconductor substrate becomes higher. Under this circumstance, it is difficult to pattern the aluminum line because of projections or protrusions occurred in a boundary thereof.
To solve such a problem, a division word driver system, which can readily avoid passing through the aluminum line in the memory cell portion, has been adopted recently.
In this system, a word driver is divided into a main word driver and a subword driver. With such a structure, the subword driver is selected by the main word line for driving with main word driver, and the selected subword driver drives the word line (subword line) for selecting the memory cell.
Referring now to
FIG. 2
, for example, when one main word line MWE is selected, subword drivers SWD
21
a
,
21
b
, and
21
c
, which are connected to the main word line MWE, are selected and activated.
The sub-word drivers SWD
21
a
,
21
b
and
21
c
are arranged at both sides of a memory cell line in parallel with a bit line pair. Herein, subword lines SW
00
~SW
13
, which are produced from the subword lines at the both sides, are arranged so as to form a comb structure with each other by sandwiching the memory cell.
For example, the subword driver SWD
21
b
is connected to subword lines SW
11
and SW
13
at right and left sides thereof. Herein, the subword lines SW
11
and SW
13
designate the memory cell at even number lines of memory cell lines arranged at right and left sides.
The subword driver SWD
21
a
is connected to subword lines SW
00
and SW
02
, which designates the memory cell corresponding to a normal rotation bit line T among bit line pairs at right and left
NEC Corporation
Nelms David
Yoha Connie C.
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