Semiconductor memory device and method for relieving defective m

Details Semiconductor memory device and method for relieving defective m Semiconductor memory device and method for relieving defective m

1999-03-16

2000-09-19

Tran, Andrew

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, G11C 700, G11C 800

Patent

active

061222070

ABSTRACT:
A semiconductor memory device includes a plurality of memory cell groups, the data for the plurality of memory cell groups being transmitted through mutually different buses, and a redundancy memory cell group common to the plurality of memory cell groups. The semiconductor memory device further includes a control circuit for transmitting data for one or more memory cells of the redundancy memory cell group in place of data for one or more defective memory cells in any of the plurality of memory cell groups. Each of the plurality of memory cell groups is provided corresponding to every different input/output terminal of the memory device, or the plurality of memory cell groups are provided corresponding to a common input/output terminal of the memory device.

REFERENCES:
patent: 4918662 (1990-04-01), Kondo
patent: 5377146 (1994-12-01), Reddy et al.
patent: 5675543 (1997-10-01), Rieger
patent: 5701270 (1997-12-01), Mohan Rao
patent: 5822257 (1998-10-01), Ogawa

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