Semiconductor memory device and method for producing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C438S257000

Reexamination Certificate

active

07622766

ABSTRACT:
Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

REFERENCES:
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patent: 6627927 (2003-09-01), Wu
patent: 6803620 (2004-10-01), Moriya et al.
patent: 2003/0008488 (2003-01-01), Iijima
patent: 2003/0155607 (2003-08-01), Kamigaki et al.
patent: 2001-156275 (2000-03-01), None
patent: 2001-326288 (2000-08-01), None
F. Arai et al., “High-Density (4.4F2) NAND Flash Technology Using Super-Shallow Channel Profile (SSCP) Engineering”, 2000 IEEE, 4 pages.
T. Kobayashi et al., “A Giga-Scale Assist-Gate (AG)-AND-Type Flash Memory Cell with 20-MB/s Programming Throughput for content-Downloading Applications”, 2001 IEEE, 4 pages.

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