Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2011-03-29
2011-03-29
Sandvik, Benjamin P (Department: 2826)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C257SE21423
Reexamination Certificate
active
07915156
ABSTRACT:
A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.
REFERENCES:
patent: 6469339 (2002-10-01), Onakado et al.
patent: 2003/0194853 (2003-10-01), Jeon
patent: 2004/0232496 (2004-11-01), Chen et al.
patent: 2005/0045941 (2005-03-01), Kurita et al.
patent: 2006/0001073 (2006-01-01), Chen et al.
patent: 2006/0194390 (2006-08-01), Imai et al.
patent: 2006/0231884 (2006-10-01), Yonemochi et al.
patent: 2006/0240619 (2006-10-01), Ozawa et al.
patent: 2007/0045711 (2007-03-01), Bhattacharyya
patent: 2007/0063256 (2007-03-01), Imai et al.
patent: 2007/0096202 (2007-05-01), Kang et al.
patent: 2007/0184615 (2007-08-01), Brazzelli et al.
patent: 2008/0014760 (2008-01-01), Murata et al.
patent: 2009/0001444 (2009-01-01), Matsuoka et al.
patent: 01-137651 (1989-05-01), None
patent: 2005-044844 (2005-02-01), None
patent: 2006-302950 (2006-11-01), None
patent: 2007-299975 (2007-11-01), None
Notification of Reasons for Rejection issued by the Japanese Patent Office in Japanese Patent Application No. 2008-044481, mailed Jun. 29, 2010 (6 pages).
A Decision of Final Rejection issued by the Japanese Patent Office in Japanese Patent Application No. 2008-044481, mailed Oct. 22, 2010 (8 pp.).
Aoyama Kenji
Iguchi Tadashi
Ito Eiji
Kiyotoshi Masahiro
Yabuki Moto
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Sandvik Benjamin P
LandOfFree
Semiconductor memory device and method for manufacturing the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device and method for manufacturing the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and method for manufacturing the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2706162