Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-23
2001-04-17
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S372000, C257S379000, C257S386000, C257S394000, C257S401000, C257S773000
Reexamination Certificate
active
06218694
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with improved degree of integration and a reduced effect from parasitic resistances in the source and drain regions.
2. Description of the Related Art
FIGS.
12
,
13
and
FIG. 14
show a semiconductor memory device of the past,
FIG. 12
showing the upper interconnect layer,
FIG. 13
showing the cross-section view thereof, and
FIG. 14
showing the condition in which the above-noted upper interconnect layer is removed.
In the above-noted drawings, the reference numeral
101
denotes a p-channel source/drain region,
111
is a source region within the source/drain region
101
,
112
is a drain region, and
113
is a gate. The upper layer aluminum interconnect
103
a
is connected to the source region
111
via a plurality of contacts
105
. The upper layer interconnect
103
b
is connected to the drain region
112
via a plurality of contacts
115
. However, as shown in
FIG. 12
, because of the existence of the interconnect
103
c
, which is provided on the same layer as the upper layer interconnects
103
a
and
103
b
, and which is provided so as to cross over the source region
111
and the drain region
112
, there are cases in which it is possible to make contact between the source and drain regions and the upper layer interconnect over only approximately 50% or less of the total gate width W, and in such cases because the resistance value of the source and drain region diffusion layers is high, if the overall gate width W becomes large, the region
117
in the drawing, this being a transistor at the edge of the source/drain region, exhibits a significant loss of capacity as a transistor, leading to the problem of a loss of writing speed.
While a proposed semiconductor device with reduced influence from parasitic resistance in the drain region is disclosed in the Japanese Unexamined Patent Publication (KOKAI) No.62-89342, according to this disclosure a plurality of contacts are provided for the purpose of reducing the resistance value of the source or the drain, and a semiconductor integrated circuit is shown in which these contacts are connected by a wire having a small resistance value. Thus, the problem being solved and the constitution of this disclosure are not the same as the present invention.
Other examples of prior art include the Japanese Unexamined Patent Publication (KOKAI) No.8-70002, according to which a backed interconnect technology reduces the interconnect resistance, and the Japanese Unexamined Patent Publication (KOKAI) No.60-200541, according to which upper and lower polysilicon films are connected via a single contact hole, so as to increase the degree of integration. However, these disclosures are also different from the present invention in terms of problem to be solved and constitution.
Accordingly, it is an object of the present invention to improve on the above-noted drawbacks in the prior art, by providing a semiconductor memory device which reduces the influence of parasitic resistance in the source and drain regions, and increases the degree of integration.
SUMMARY OF THE INVENTION
In order to achieve the above-noted objects, the present invention adopts the following basic technical constitution.
Specifically, the first aspect of a semiconductor memory device according to the present invention is a semiconductor memory device that has a source region formed in the shape of a band, a drain region formed in the shape of a band in opposition to the source region, a first interconnect which is provided in a layer above the source region and which makes connection thereto, a second interconnect which is provided in a layer above the drain region and which makes connection thereto and which is provided on the same layer as the first interconnect, and a third interconnect, which is provided on the same layer as the first and second interconnects and which is provided so as to laterally cross the source and drain regions, this semiconductor memory device further having a first contact region that is provided with a plurality of contacts in the source/drain region on one side of the third interconnect, and a second contact region that is provided with a plurality of contacts in the source/drain region on the other side of the third interconnect. The source region is connected via the contacts of the first contact region to the first interconnect, and the drain region is connected via the contacts of the first contact region to the second interconnect. An interconnect layer having a resistance value that is lower than the above-noted source/drain region is provided below the third interconnect, along the source/drain region, the source region of the first contact region and the source region of the second contact region being connected by an interconnect layer having a lower resistance value than the source region, and the drain region of the first contact region and the drain region of the second contact region being connected by an interconnect layer having a lower resistance than the drain region.
The second aspect of a semiconductor memory device according to the present invention is a semiconductor memory device that has a source region formed in the shape of a band, a drain region formed in the shape of a band in opposition to the source region, a first interconnect which is provided in a layer above the source region and which makes connection thereto, a second interconnect which is provided in a layer above the drain region and which makes connection thereto and which is provided on the same layer as the first interconnect, and a third interconnect, which is provided on the same layer as the first and second interconnects and which is provided so as to laterally cross the source and drain regions, this semiconductor memory device further having a first contact region that is provided with a plurality of contacts in the source/drain region on one side of the third interconnect, and a second contact region that is provided with a plurality of contacts in the source/drain region on the other side of the third interconnect. The source region is connected via the contacts of the first contact region to the first interconnect, and the drain region is connected via the contacts of the second contact region to the second interconnect. An interconnect layer having a resistance value that is lower than the above-noted source/drain region is provided below the third interconnect, along the source/drain region, the source region of the first contact region and the source region of the second contact region being connected by an interconnect layer having a lower resistance value than the source region, and the drain region of the first contact region and the drain region of the second contact region being connected by an interconnect layer having a lower resistance than the drain region.
In the third aspect of a semiconductor memory device according to the present invention, a plurality of the above-noted contact regions are provided, these contact regions each being connected by an interconnect layer that has a resistance value lower than the source/drain region.
REFERENCES:
patent: 5998846 (1999-12-01), Jan et al.
patent: 57-49254 (1982-03-01), None
patent: 60-200541 (1985-10-01), None
patent: 61-133664 (1986-06-01), None
patent: 62-89342 (1987-04-01), None
patent: 8-7002 (1996-03-01), None
patent: 10-27853 (1998-01-01), None
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
Wojciechowicz Edward
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