Semiconductor memory device and method for its test

Details Semiconductor memory device and method for its test Semiconductor memory device and method for its test

2001-10-12

2003-07-08

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S222000

Reexamination Certificate

active

06590815

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor memory device, and more specifically to a semiconductor memory device including refresh test circuit for subjecting redundancy memory cells to a refresh test and a method for its test.
BACKGROUND OF THE INVENTION
Due to a large bit capacity, a semiconductor memory device such as a dynamic random access memory (DRAM) is typically used as a main memory of a computer. A memory cell on a DRAM includes a data holding capacitor and a data transfer transistor. Each memory cell can store one bit of data by storing a quantity of electric charge as determined by the logic value of the stored data.
Over time, the stored electric charge can leak away from the memory cell and the integrity of the data can be compromised. The stored electric charge typically leaks away due to junction leakage current and subthreshold leakage current through the data transfer transistor.
In order to improve data integrity, refresh operations are performed to restore the electric charge stored in each memory cell.
A self refresh operation is one method used to restore the electric charge in each memory cell. In this case, the refresh is automatically executed for all the word lines of a memory cell array by using a counter having a predetermined count period and an internally generated address.
A CBR (CAS before RAS) refresh is another method used to restore the electric charge in each memory cell. In this case, a CBR command is input and an address counter provides the row address so that a word line is selected and memory cells are refreshed. CBR commands are continuously input until all word lines have been selected.
Each memory cell must be refreshed within a predetermined time period according to the specification of the DRAM. Thus, it is necessary that a refresh test is performed to determine if a DRAM satisfies the refresh period.
If the refresh test identifies a word line corresponding to a memory cell that fails the refresh test, a redundant word line can be used to replace the defective memory cell or row of memory cells. In this way, the overall manufacturing yield can be improved.
It is thus desirable that the same refresh test be performed for memory cells connected to the redundant word lines as is performed in the normal memory cells.
However, before fuse trimming (or blowing) is performed, an address of the redundant word line is not defined. This can make it difficult to perform a CBR refresh test for a memory cell that corresponds to the redundant word line in the same manner as an ordinary word line. This reason will now be described with reference to FIG.
1
.
Referring now to
FIG. 1
, a block schematic diagram of a conventional DRAM is set forth and given the general reference character
100
. Conventional DRAM
100
is illustrated from the viewpoint of performing a CBR refresh test.
Conventional DRAM
100
includes a x1 bit input/output construction and a memory cell region M having a 2 Mbit capacity and redundant word lines.
A command circuit
3
receives and decodes an external command and outputs command signals such as a CBR reference command signal RF, a RAS system activation signal ACTX, and a CAS system activation signal ACTY in accordance with the received command. A counter activation circuit
5
receives the CBR refresh command signal and outputs a CBR refresh counter activation signal ACBR accordingly.
CBR refresh counter
4
is activated by CBR refresh counter activation signal ACBR to count an input CBR command and output address counter signals (CNT
0
to CNT
11
).
Address input circuit
1
shapes and translates externally received address signal (A
0
to A
11
) and outputs internal address signals (IA
0
to IA
11
).
X address buffer
2
multiplexes between internal address signals (IA
0
to IA
11
) and address counter signals (CNT
0
to CNT
11
) based upon RAS system activation signal ACTX to provide internal X address signals (XA
0
to XA
11
).
X predecoder
6
decodes internal x address signals (XA
0
to XA
11
) and outputs word line select signals (XP
0
to XP
4095
). X decoder
7
selects and provides a boosted voltage to one of word lines (W
0
to W
4095
) based upon word select signals (XP
0
to XP
4095
).
Activation circuit
12
receives RAS system activation signal ACTX and outputs X address latch signal XLAT. X redundancy circuit
8
latches internal X address signals (XA
0
to XA
11
) based upon X address latch signal XLAT and outputs internal redundant word line select signals (XRD
0
to XRD
63
) in accordance with the value of internal X address signals (XA
0
to XA
11
) and the value of fuse structures forming a ROM (read only memory) within X redundancy circuit
8
. In this way, ordinary word lines can be replaced with redundant word lines.
In the redundancy test mode, redundancy test control circuit
11
activates a redundancy test mode activation signal TREDX. When redundancy test mode activation signal TREDX is activated, X redundancy control circuit
9
decodes internal x address signals (XA
0
to XA
11
) to select one of redundant word line select signals (RXW
0
to RXW
63
) and output a redundancy circuit use signal XRDV to deactivate of X predecoder
6
.
X redundancy decoder
10
selects one of redundant word lines (RW
0
to RW
63
) based on the redundant word line select signals (RXW
0
to RXW
63
) and provides a boosted level on the one selected.
Y address buffer
13
outputs internal Y address signal (YA
0
to YA
8
) based upon internal address signals (IA
0
to IA
8
) when an active CAS system activation signal ACTY is received. Y-decoder
14
provides Y switch signals (Y
0
to Y
511
) that select sense amplifiers corresponding to respective bit lines.
Memory cell region M is arranged to include 512 bit lines (bit line pairs), 4096 ordinary word lines and 64 redundant word lines. The bit lines are arranged perpendicular to and intersect the ordinary word lines and redundant word lines.
Referring now to
FIG. 2
, a block schematic diagram illustrating the arrangement of memory cell region M of conventional DRAM
100
is set forth.
Memory cell region M is divided into eight plates (P
0
to P
7
). Each plate (P
0
to P
7
) includes 512 word lines. For example, plate P
0
includes word lines (W
0
(#000) to W
511
(#1FF)), plate P
1
includes word lines (W
512
(#200) to W
1023
(#3FF)), etc. and plate P
7
includes word lines (W
3584
(#D00) to W
4095
(#FFF)), where # indicates a word line address in hexidecimal notation.
Each plate (P
0
to P
7
) includes 8 redundant word lines. For example, plate P
0
includes redundant word lines (RW
0
(#000) to RW
7
(#007)), plate P
1
includes redundant word lines (RW
8
(#200) to RW
15
(#207)), etc., and plate P
7
includes redundant word lines (RW
56
(#E00) to RW
63
(#E07)), where # indicates a word line address in hexidecimal notation representing addresses represented by lower addresses (XA
0
, XA
1
, and XA
2
) and plate select addresses (XA
9
, XA
10
, and XA
11
).
Redundant word lines (RW
0
to RW
7
) are used as replacement word lines for plate P
0
and redundancy word lines (RW
8
to RW
15
) are used as replacement word lines for plate P
1
, etc.
In plate P
0
, sense amplifier circuit
200
and bit lines (B
0
-
0
to B
0
-
511
) are provided in a normal cell array NM and a redundant cell array RD. Also, in plate P
1
, sense amplifier circuit
201
and bit lines (B
1
-
0
to B
1
-
511
) are provided in a normal cell array NM and a redundant cell array RD. Likewise, in plates (P
2
to P
7
), respectively, there are sense amplifier circuits and 512 bit lines individually provided in a memory cell array NM and redundant cell array RD. Plates (P
2
to P
7
) are not shown in detail in order to avoid unduly cluttering the figure.
In memory cell array NM, a memory cell NC is formed at predetermined intersections between word lines and bit lines.
In the same fashion, in redundant cell array RD, a redundant memory cell RC is formed at predetermined intersections between redunda

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