Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-04-05
2001-07-17
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230030, C365S230040
Reexamination Certificate
active
06262940
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to memory hardware, and more particularly, to a semiconductor memory device for improving the transmission data rate of a data input and output bus, and a memory module including such a device.
Memory modules are circuit boards designed to mount memory chips. Generally, memory modules are easily inserted into and extracted from a connector within the computer system. Memory modules are driven by being connected to all necessary power sources, ground power sources, and logic signals.
Memory modules typically include a plurality of RAM chips mounted on a print circuit board. DRAM, SRAM, or video RAM can be used in various applications depending on the requirements. DRAMs are generally cheaper and have a larger capacity than SRAMs, so that they have been widely used as essential elements such as the main memory of computer systems. SRAM and video RAM modules are more restricted in use and so they are respectively applied to special purposes such as for a cache memory or for a video frame buffer.
Many techniques are used for fast operation of a DRAM. For example, fast access modes such as page mode, a static column mode, and a nibble mode are used. Characteristics such as enhanced DRAMs or RAMBUS DRAMs are also used. Accordingly, memory modules using various different RAM memories are required to improve the bandwidth of a memory, i.e., the speed of information that can be exchanged with a memory.
The appearance of synchronous DRAMs (SDRAMs) is one of the newest and the most important improvements in the area of memory access speed and bandwidth. SDRAMs are different from asynchronous DRAMs in that they operate in synchronization with a clock signal. Typically, SDRAMs have predetermined sections where data read from a memory is effective. Data is essentially read in response to a clock signal combined with a read command provided to SDRAMs. In other words, SDRAMs output the effective data of a memory cell after a read command is issued, and maintain the data throughout a predetermined period. This predetermined period is called “valid data window.” Thus, the SDRAMs provide data within the valid data window in accordance with a continuous clock signal. A method of reading data from a module including an SDRAM has been disclosed in U.S. Pat. No. 5,577,236, the contents of which are hereby incorporated by reference in their entirety.
According to this U.S. patent, when data is read from a memory bank of an SDRAM, a memory controller provides an optimal clock signal to compensate for the delay of read data due to a line load and a process variation upon manufacture of chips and cards. SDRAMs perform reading/writing operations in accordance with the rising edge of the optimal clock signal. This means that memory cell data is read from an SDRAM and transferred to a data input and output bus during one cycle of a clock signal provided to the SDRAM.
As a result, the transmission data rate of the data input and output bus is defined by a clock cycle in the U.S. Pat. No. 5,577,236. In other words, the transmission data rate of the data input and output bus is determined according to the operation of a single data rate SDRAM (SDR SDRAM). Therefore, the transmission data rate described above is not sufficient to satisfy the operation of a memory module that requires a data input and output bus having a high data rate.
SUMMARY OF THE INVENTION
To solve the above problem, it is an object of the present invention to provide a semiconductor memory device by which the transmission data rate of a data input and output bus is improved.
It is another object of the present invention to provide a memory module having such a semiconductor memory device.
Accordingly, to achieve the first object, the present invention provides a semiconductor memory device that comprises a data bus line, a clock signal generator for receiving a system clock signal and generating first and second clock signals, a first set of synchronous memory devices connected to the data bus line for outputting first memory cell data to the data bus line in synchronization with the first clock signal, and a second set of clock synchronous memory devices connected to the data bus line for outputting second memory cell data to the data bus line in synchronization with the second clock signal.
Preferably the first and second clock signals are generated such that the first and second set of synchronous memory devices are not connected to the data bus line at the same time. Also, the first clock signal is preferably substantially identical to the system clock signal, and the second clock signal is preferably delayed by a predetermined time interval with respect to the system clock signal. The second clock signal is preferably delayed by a predetermined time interval such that the second clock signal it is the inverse of the system clock signal.
The first and second sets of synchronous memory devices preferably have a valid data window that is smaller than the predetermined time interval.
The semiconductor memory device may further comprise an address/command driver for providing address and command signals to the first and second sets of synchronous memory devices.
To achieve the second object, the present invention provides a memory module that comprises a printed circuit board having an electrical connector including a data bus line, a first set of synchronous memory devices arranged on the printed circuit board and connected to the data bus line, a second set of synchronous memory devices arranged on the print circuit board and connected to the data bus line, and a clock signal generator electrically connected to the first and second set of synchronous memory devices, for receiving a system clock signal from the electrical connector and generating a first clock signal and a second clock signal. The first memory data in the first set of synchronous memory devices and second memory data in the second set of synchronous memory devices are alternately output to the data bus line.
The first clock signal is preferably matched with the received clock signal, while the second clock signal is preferably delayed with respect to the received clock signal for half the period of the received clock signal.
The memory module may further comprise an address/command driver connected to a first and second sets of synchronous memory devices, for receiving a memory address of one of the first or second set of synchronous memory devices and a command for directing an operation mode of the one of the first or second set of synchronous memory devices, from the electrical connector. The address/command driver preferably starts activating the memory devices before the first and second clock signals are generated.
The synchronous memory devices preferably have a valid data window that is smaller than half the period of the clock signal. The synchronous memory devices preferably enlarge the main memory of the memory module, and increase the data bandwidth of the memory module.
As described above, the present invention includes SDRAM sets which synchronize with a plurality of clocks, respectively, thus improving the transmission data rate of a data input and output bus and the bandwidth of a memory module.
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Choi Hoon
Kim Sei-jin
Maesako Taketo
Jones Volentine, L.L.C.
Nguyen Tan T.
Samsung Electronics Co,. Ltd.
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