Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1997-08-08
2001-06-19
Downs, Robert W. (Department: 2165)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C714S711000
Reexamination Certificate
active
06249850
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device having a protecting function against illegal copying, and more particularly to an electrically programmable mask ROM having redundancy cells and a method for protecting the same from illegal copying.
The memory cell array of a semiconductor memory device, for example, a mask ROM (Read Only Memory) is constructed by arranging memory cells formed of MOS transistors in a matrix form, connecting the gates of the memory cells on each row to a corresponding one of a plurality of word lines extending in the row direction, connecting the drains of the MOS transistors on each column to a corresponding one of a plurality of bit lines extending in the column direction, and grounding the sources of the MOS transistors. As a method for writing data into the memory cell, (a) a diffusion layer programming system, (b) ion-implantation programming system, (c) contact programming system and the like are known, information of “0”, “1” is set to correspond to the presence or absence of a MOS transistor, the depletion type or enhancement type of a MOS transistor, or the presence or absence of a contact hole, and data is written by using a photomask in the course of the manufacturing process. The operation of reading out stored data is effected by selecting and charging one of the bit lines, selecting one of the word lines and setting the same to a high potential level, and determining “0” or “1” of stored information according to whether or not the bit line is discharged via a MOS transistor (memory cell) which is connected to both of the selected bit line and selected word line.
Generally, in the above mask ROM, redundancy cells which are used instead of defective memory cells when the defective memory cells are present are provided to relieve the memory. The redundancy cell is constructed by an electrically programmable memory element and data for the defective memory cell is stored therein. When the defective cell is accessed, data is read out from the redundancy cell instead of the defective cell, thus compensating for the defect of the cell.
However, with the above construction, data stored in the memory cell array can be easily read out by sequentially incrementing the ROM address by use of a ROM writer or personal computer. Therefore, there occurs a problem that the stored data can be easily copied by writing readout data into a storage medium such as a hard disk or floppy disk.
Therefore, various types of circuits and copy protect methods for providing a protect function against the illegal copying are proposed. For example, the techniques disclosed in Jap. Pat. Appln. KOKAI Publications Nos. 1-173244, 2-42551, 4-74240 and 7-262000 are known. However, if an attempt is made to attain a sufficient protection effect, a problem that the circuit scale is increased occurs.
BRIEF SUMMARY OF THE INVENTION
Accordingly, a first object of this invention is to provide a semiconductor memory device capable of protecting stored data from illegal copying without causing an increase in the circuit scale and chip occupancy area.
Further, a second object of this invention is to provide a stored data copying method for a semiconductor memory device, for making copied data substantially invalid even if stored data is copied by illegal means.
The first object of this invention can be attained by a mask ROM comprising memory cells in which data items are written by use of a mask; electrically programmable redundancy cells, data to be written into defective memory cells being written in respective ones of the redundancy cells when the defective memory cells are present and error data being stored in non-use cells among the redundancy cells; access means for accessing the redundancy cell in which the error data is written when one of access inhibition addresses is accessed; and output means for outputting the error data from the redundancy cell accessed by the access means.
Further, the first object of this invention can be attained by a semiconductor memory device comprising a memory cell array having data previously stored therein; first access means for accessing the memory cell array; output means for amplifying and outputting data read out from a memory cell accessed by the first access means; redundancy cells selectively used instead of defective cells to compensate for the defects of the defective cells when the defective cells are present in the memory cell array; and second access means for accessing the redundancy cell instead of the defective cell when the address of the defective cell is accessed; wherein error data is written into non-use cells among the redundancy cells, the addresses of the second access means corresponding to the non-use cells in which the error data is written are set as access inhibition addresses, and the error data written in the non-use cell is output from the output means when the access inhibition address is accessed.
With the above construction, since the protect function is realized by use of the non-use cells among the redundancy cells, the stored data can be protected from illegal copying without increasing the circuit scale and chip occupancy area. Further, since true data and error data are output in a mixed form when the access inhibition address is accessed, readout data cannot be substantially utilized even if the stored data is copied.
The second object of this invention is attained by an illegal copying preventing method for a mask ROM having electrically programmable redundancy cells, comprising the steps of writing error data into non-use cells of the redundancy cells; attaching access inhibition addresses to the respective non-use cells in which the error data is written; and outputting the error data from the redundancy cell when the access inhibition address is accessed.
The second object of this invention is attained by a copying method for copying stored data in a semiconductor memory device which has a memory space including a first area in which a starting program for starting the copying process is written, a second area in which an application software is written, and a third area in which a data base is written, and a redundancy space including a first area in which error data is stored in a non-use area and a second area in which a password and a space address of error data are stored in the non-use area; and in which an address in the first area of the memory space is attached to the password and the space address of the error data in the redundancy space and an address in the third area of the memory space is attached to the error data; comprising a first step of starting the program for copying and effecting the initialization and copy checking processes; a second step of inputting a password; a third step of determining whether or not the input password coincides with a previously stored password; a fourth step of determining whether or not an address to be accessed corresponds to the space of the error data when it is determined in the third step that the passwords coincide with each other; a fifth step of effecting the copying operation when it is determined in the fourth step that the address does not correspond to the space of the error data; a sixth step of determining whether or not the address is a final address when it is determined in the fourth step that the address corresponds to the space of the error data or after the copying operation of the fifth step is terminated and terminating the copying process when the address is detected to be a final address; a seventh step of incrementing the address by “1” when it is determined in the sixth step that the address is not a final address and returning the process to the fourth step; an eighth step of effecting the copying operation when it is determined in the third step that the passwords do not coincide with each other; a ninth step of determining whether or not the address of data copied in the eighth step is a final address and terminating the copying process when the address is detected to be a final a
Downs Robert W.
Hogan & Hartson LLP.
Kabushiki Kaisha Toshiba
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